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参数资料
| 型号： | C9832HT |
| 英文描述： | Up to 5A ULDO linear regulator |
| 中文描述： | CPU系统时钟发生器|采用TSSOP | 56PIN |塑料 |
| 文件页数： | 2/24页 |
| 文件大小： | 169K |
| 代理商： | C9832HT |
C9832H
High Performance Pentium 4 Clock Synthesizer
Cypress Semiconductor Corporation
525 Los Coches St.
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
http://www.cypress.com
Document#: 38-07109 Rev. **
5/24/2001
Page 2 of 24
Approved Product
Pin Description
PIN
2
3
NAME
PWR
I/O
I
O
Description
XIN
XOUT
Oscillator Buffer Input. Connect to a crystal or to an external clock.
Oscillator Buffer Output. Connect to a crystal. Do not connect when an
external clock is applied at XIN.
Differential host output clock pairs. See the frequency table on page one
of this data sheet for frequencies and functionality.
PCI Clock Outputs. See Frequency Table on page one of this data sheet.
VDD
52, 51, 49,
48, 45, 44
10, 11, 12,
16, 17, 18
5, 6, 7
CPU, CPU/
(0:2)
PCI(0:2, 4:6)
VDD
O
VDDP
O
PCIF (0:2)
VDD
O
33Mhz PCI clocks, which are
÷
2 copies of 66IN or 3V66 clocks, may be
free running (not stopped when PCI_STP# is asserted low) or may be
stoppable depending on the programming of I2C register Byte3, Bits
(3:5).
Early PCI clock. Leads all other PCI clocks by 1ns typ.
Buffered Output copy of the device’s XIN clock.
Current reference programming input for CPU buffers. A resistor is
connected between this pin and VSSIREF. See CPU Clock current Select
Table in page 18 of this data sheet.
Qualifying input that latches S (0:2) and MULT0. When this input is at a
logic low, the S (0:2) and MULT0 are latched
Fixed 48MHz USB Clock Outputs.
Fixed 48MHZ DOT Clock Outputs.
3.3 Volt 66 MHz fixed frequency clock.
3.3 volt clock selectable with I
2
C byte0, Bit5, when Byte5, Bit5. When
Byte 0 Bit 5 is at a logic 1, then this pin is a 48M output clock. When
byte0, Bit5 is a logic 0, then this is a 66M output clock (default).
This pin is a power down mode pin. A logic low level causes the device
to enters a power down state. All internal logic is turned off except for the
I
2
C logic. All output buffers are stopped. See the Power Down section of
this data sheet.
Programming input selection for CPU clock current multiplier. See CPU
Clock Current Select Function Table.
Frequency Select Inputs. See Frequency Table on page 1.
Serial Data Input. Conforms to the Philips I
2
C specification of a Slave
Receive/Transmit device. It is an input when receiving data. It is an open
drain output when acknowledging or transmitting data. See application
note AN-0022
Serial Clock Input. Conforms to the Philips I
2
C specification. See
application note AN-0022.
Frequency Select input. See Frequency Table on page 1. This is a Tri
level input, which is driven high, low or driven to an intermediate level.
PCI Clock Disable Input. When asserted low, PCI (0:6) clocks are
synchronously disabled in a low state. This pin does not effect PCIF (0:2)
clocks’ outputs if they are programmed to be PCIF clocks via the device’s
I
C interface.
13
56
42
PCIE
REF
IREF
VDD
VDD
VDD
O
O
I
28
VTT_PG#
VDD
I
39
38
33
35
48MUSB
48MDOT
3V66_0
3V66_1/VCH
VDD48
VDD48
VDD
VDD
O
O
O
O
25
PD#/
VDD
PU
I
43
MULT0
I
55, 54
29
S(0,1)
SDATA
I
I
I
I
30
SCLK
I
I
40
S2
VDD
I
T
I
34
PCI_STP#
VDD
PU
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