参数资料
| 型号： | CDB5460AU |
| 厂商： | Cirrus Logic Inc |
| 文件页数： | 14/54页 |
| 文件大小： | 0K |
| 描述： | EVALUATION BOARD FOR CS5460A |
| 标准包装： | 1 |
| 主要目的： | 电源管理，电度表/功率表 |
| 嵌入式： | 是，MCU，8 位 |
| 已用 IC / 零件： | CS5460A |
| 主要属性： | 1 相电流和电压监控 |
| 次要属性： | 图形用户接口，SPI? 和 USB 接口 |
| 已供物品： | 板，线缆，软件 |
| 相关产品： | CS5460A-BSZR-ND - IC ENERGY METERING 1PHASE 24SSOP 598-1701-ND - IC PWR/ENERGY 1PH BIDIR 24SSOP 598-1700-ND - IC PWR/ENERGY 1PH BIDIR 24SSOP 598-1094-5-ND - IC ENERGY METERING 1PHASE 24SSOP |
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CS5460A
full-scale. Note that the 24-bit signed output words
are expressed in two’s complement format. The
24-bit data words in the CS5460A output registers
Output Code
Input Voltage (DC) (hexidecimal)
Output Code
(decimal)
represent values between 0 and 1 (for unsigned
output registers) or between -1 and +1 (for signed
output registers). A register value of 1 represents
the maximum possible value. Note that a value of
1.0 is never actually obtained in the registers of the
CS5460A. As an illustration, in any of the signed
+250 mV
14.9 nV to 44.7 nV
-14.9 nV to 14.9 nV
-44.7 nV to -14.9 nV
-250 mV
7FFFFF
000001
000000
FFFFFF
800000
8388607
1
0
-1
-8388608
output registers, the maximum register value is
[(2^23 - 1) / (2^23)] = 0.999999880791. After each
A/D conversion, the CRDY bit will be asserted in
the Status Register, and the INT pin will also be-
come active if the CRDY bit is unmasked (in the
Mask Register). The assertion of the CRDY bit in-
dicates that new instantaneous 24-bit voltage and
current samples have been collected, and these
two samples have also been multiplied together to
provide a corresponding instantaneous 24-bit pow-
er sample.
Table 1 conveys the typical relationship between
the differential input voltage (across the “+” and “-”
input pins of the voltage channel input) and the cor-
responding output code in the Instantaneous Volt-
age Register. Note that this table is applicable for
the current channel if the current channel’s PGA
gain is set for the “10x” gain mode.
0.5
0.0
-0.5
-1.0
-1.5
-2.0
Table 1. Differential Input Voltage vs. Output Code
The V RMS , I RMS , and energy calculations are up-
dated every N conversions (which is known as 1
“ computation cycle ”), where N is the value in the
Cycle Count Register. At the end of each computa-
tion cycle, the DRDY bit in the Mask Register will
be set, and the INT pin will become active if the
DRDY bit is unmasked.
DRDY is set only after each computation cycle has
completed, whereas the CRDY bit is asserted after
each individual A/D conversion. Bits asserted by
the CS5460A must be cleared before being assert-
ed again. If the Cycle Count Register value (N) is
set to 1, all output calculations are instantaneous,
and DRDY will indicate when instantaneous calcu-
lations are finished, just like the CRDY bit. For the
RMS results to be valid, the Cycle-Count Register
must be set to a value greater than 10.
The computation cycle frequency is derived from
the master clock, and has a value of
(MCLK/K)/(1024*N). Under default conditions, with
0.5
0
-0.5
-1
-1.5
-2
-2.5
0
200
400
600
800
1000 1200 1400
1600 1800 2000
-2.5
0
200
400
600
800
1000 1200 1400 1600
1800 2000
14
Frequency (Hertz)
Figure 4. Voltage Input Filter Characteristics
Frequency (Hertz)
Figure 5. Current Input Filter Characteristics
DS487F5
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相关代理商/技术参数 |
参数描述 |
|---|---|
| CDB5460AU-Z | 制造商:Cirrus Logic 功能描述:PB-FREEEVAL BOARD FOR CS5460 - Bulk |
| CDB5461 | 制造商:Cirrus Logic 功能描述:EVAL BD FOR CS5461 - Bulk |
| CDB5461A | 功能描述:EVAL BOARD FOR CS5461 RoHS:否 类别:编程器，开发系统 >> 过时/停产零件编号 系列:- 标准包装:1 系列:- 类型:MCU 适用于相关产品:Freescale MC68HC908LJ/LK（80-QFP ZIF 插口） 所含物品:面板、缆线、软件、数据表和用户手册 其它名称:520-1035 |
| CDB5461AU | 功能描述:数据转换 IC 开发工具 Eval Bd Sngl-Phase Pow/Energy RoHS:否 制造商:Texas Instruments 产品:Demonstration Kits 类型:ADC 工具用于评估:ADS130E08 接口类型:SPI 工作电源电压:- 6 V to + 6 V |
| CDB5461AU-Z | 制造商:Cirrus Logic 功能描述:PB-FREEEVAL BOARD FOR CS5461 WITH USB - Bulk |
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