参数资料
型号: CDB5460AU
厂商: Cirrus Logic Inc
文件页数: 52/54页
文件大小: 0K
描述: EVALUATION BOARD FOR CS5460A
标准包装: 1
主要目的: 电源管理,电度表/功率表
嵌入式: 是,MCU,8 位
已用 IC / 零件: CS5460A
主要属性: 1 相电流和电压监控
次要属性: 图形用户接口,SPI? 和 USB 接口
已供物品: 板,线缆,软件
相关产品: CS5460A-BSZR-ND - IC ENERGY METERING 1PHASE 24SSOP
598-1701-ND - IC PWR/ENERGY 1PH BIDIR 24SSOP
598-1700-ND - IC PWR/ENERGY 1PH BIDIR 24SSOP
598-1094-5-ND - IC ENERGY METERING 1PHASE 24SSOP
CS5460A
Voltage
Reference Output
Voltage
Reference Input
Differential
11
12
15,16
VREFOUT - The on-chip voltage reference is output from this pin. The voltage reference
has a nominal magnitude of 2.5 V and is reference to the VA- pin on the converter.
VREFIN - The voltage input to this pin establishes the voltage reference for the on-chip
modulator.
IIN+, IIN- - Differential analog input pins for current channel.
Current Inputs
Power Supply Connections
Positive
Digital Supply
Digital Ground
Negative
Analog Supply
Positive
Analog Supply
Power Fail Monitor
RESET
Other
No Connection
52
3
4
13
14
17
19
18
VD+ - The positive digital supply is nominally +5 V ±10% relative to DGND.
DGND - The common-mode potential of digital ground must be equal to or above the
common-mode potential of VA-.
VA- - The negative analog supply pin must be at the lowest potential.
VA+ - The positive analog supply is nominally +5 V ±10% relative to VA-.
PFMON - The power fail Monitor pin monitors the analog supply. Typical threshold level
(PMLO) is 2.45 V with respect to the VA- pin. If PFMON voltage threshold is tripped, the
LSD (low-supply detect) bit is set in the Status Register. Once the LSD bit has been set,
it will not be able to be reset until the PFMON voltage increases ~100 mV (typical) above
the PMLO voltage. Therefore, there is hysteresis in the PFMON function.
Reset - When reset is taken low, all internal registers are set to their default states.
NC - No connection. Pin should be left floating.
DS487F5
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