参数资料
| 型号： | CDB5460AU |
| 厂商： | Cirrus Logic Inc |
| 文件页数： | 16/54页 |
| 文件大小： | 0K |
| 描述： | EVALUATION BOARD FOR CS5460A |
| 标准包装： | 1 |
| 主要目的： | 电源管理，电度表/功率表 |
| 嵌入式： | 是，MCU，8 位 |
| 已用 IC / 零件： | CS5460A |
| 主要属性： | 1 相电流和电压监控 |
| 次要属性： | 图形用户接口，SPI? 和 USB 接口 |
| 已供物品： | 板，线缆，软件 |
| 相关产品： | CS5460A-BSZR-ND - IC ENERGY METERING 1PHASE 24SSOP 598-1701-ND - IC PWR/ENERGY 1PH BIDIR 24SSOP 598-1700-ND - IC PWR/ENERGY 1PH BIDIR 24SSOP 598-1094-5-ND - IC ENERGY METERING 1PHASE 24SSOP |
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CS5460A
result from one of several result registers. The first
8 SCLKs are used to clock in the command to de-
termine which register is to be read. The last 24
SCLKs are used to read the desired register. After
reading the data, the serial port remains in the ac-
tive state , and waits for a new command to be is-
sued. (See Section 3 for more details on reading
register data from the CS5460A).
2.2.3 Continuous Computation Cycles
(C=1)
When C = 1, the CS5460A will perform conversions
in ‘continuous computation cycles’ data acquisition
mode. Based on the information provided in the Cy-
cle Count Register, computation cycles are repeat-
edly performed on the voltage and current channels
(after every N conversions). Computation cycles
cannot be started/stopped on a ‘per-channel’ basis.
After each computation cycle is completed, DRDY
is set. Thirty-two SCLKs are then needed to read a
register. The first 8 SCLKs are used to clock in the
command to determine which results register is to
be read. The last 24 SCLKs are used to read out the
24-bit calculation result. While in this acquisition
mode, the designer/programmer may choose to ac-
quire (read) only those calculations required for
their particular application, as DRDY repeatedly in-
dicates the availability of new data. Note again that
the MCU firmware must reset the DRDY bit to “0”
before it can be asserted again.
Referring again to Figure 3, note that within the
Irms and Vrms data paths, prior to the square-root
operation, the instantaneous voltage/current data
is low-pass filtered by a Sinc 2 filter. Then the data
is decimated to every Nth sample. Because of the
Sinc 2 filter operation, the first output for each chan-
nel will be invalid (i.e. all RMS calculations are in-
valid in the ‘single computation cycle’ data
acquisition mode and the first RMS calculation re-
sults will be invalid in the ‘continuous computation
cycles’ data acquisition mode). However, all ener-
gy calculations will be valid since energy calcula-
tions do not require this Sinc 2 operation.
If the ’Start Conversions’ command is issued to the
ly) ), and if the ‘C’ bit in this command is set to a val-
ue of ‘1’, the device will remain in its active state .
Once commanded into continuous computation
16
cycles data acquisition mode, the CS5460A will
continue to perform A/D conversions on the volt-
age/current channels, as well as all subsequent
calculations, until:
1) the ‘Power-Up/Halt’ command is received
through the serial interface, or
2) loss of power, or
3) the RS bit in the Configuration Register is as-
serted (‘software reset’), or
4) the /RESET pin is asserted and then de-assert-
ed (‘hardware reset’).
2.3 Basic Application Circuit
Configurations
Figure 6 shows the CS5460A connected to a ser-
vice to measure power in a single-phase 2-wire
system operating from a single power supply. Note
that in this diagram the shunt resistor used to mon-
itor the line current is connected on the “Line” (hot)
side of the power mains. In most residential power
metering applications, the power meter’s cur-
rent-sense shunt resistor is intentionally placed on
the ‘hot’ side of the power mains in order to help
detect any attempt by the subscriber to steal pow-
er. In this type of shunt-resistor configuration, note
that the common-mode level of the CS5460A must
be referenced to the hot side of the power line. This
means that the common-mode potential of the
CS5460A will typically oscillate to very high posi-
tive voltage levels, as well as very high negative
voltage levels, with respect to earth ground poten-
tial. The designer must therefore be careful when
attempting to interface the CS5460A’s digital out-
put lines to an external digital interface (such as a
LAN connection or other communication network).
Such digital communication networks may require
that the CMOS-level digital interface to the meter is
referenced to an earth-ground. In such cases, the
CS5460A’s digital serial interface pins must be iso-
lated from the external digital interface, so that
there is no conflict between the ground references
of the meter and the external interface. The
CS5460A and associate circuitry should be en-
closed in a protective insulated case when used in
this configuration, to avoid risk of harmful electric
shock to humans/animals/etc.
Figure 7 shows how the same single-phase
two-wire system can be metered while achieving
DS487F5
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| CDB5467U | BOARD EVAL FOR CS5467 ADC |
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相关代理商/技术参数 |
参数描述 |
|---|---|
| CDB5460AU-Z | 制造商:Cirrus Logic 功能描述:PB-FREEEVAL BOARD FOR CS5460 - Bulk |
| CDB5461 | 制造商:Cirrus Logic 功能描述:EVAL BD FOR CS5461 - Bulk |
| CDB5461A | 功能描述:EVAL BOARD FOR CS5461 RoHS:否 类别:编程器，开发系统 >> 过时/停产零件编号 系列:- 标准包装:1 系列:- 类型:MCU 适用于相关产品:Freescale MC68HC908LJ/LK（80-QFP ZIF 插口） 所含物品:面板、缆线、软件、数据表和用户手册 其它名称:520-1035 |
| CDB5461AU | 功能描述:数据转换 IC 开发工具 Eval Bd Sngl-Phase Pow/Energy RoHS:否 制造商:Texas Instruments 产品:Demonstration Kits 类型:ADC 工具用于评估:ADS130E08 接口类型:SPI 工作电源电压:- 6 V to + 6 V |
| CDB5461AU-Z | 制造商:Cirrus Logic 功能描述:PB-FREEEVAL BOARD FOR CS5461 WITH USB - Bulk |
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