参数资料
型号: CDB5460AU
厂商: Cirrus Logic Inc
文件页数: 47/54页
文件大小: 0K
描述: EVALUATION BOARD FOR CS5460A
标准包装: 1
主要目的: 电源管理,电度表/功率表
嵌入式: 是,MCU,8 位
已用 IC / 零件: CS5460A
主要属性: 1 相电流和电压监控
次要属性: 图形用户接口,SPI? 和 USB 接口
已供物品: 板,线缆,软件
相关产品: CS5460A-BSZR-ND - IC ENERGY METERING 1PHASE 24SSOP
598-1701-ND - IC PWR/ENERGY 1PH BIDIR 24SSOP
598-1700-ND - IC PWR/ENERGY 1PH BIDIR 24SSOP
598-1094-5-ND - IC ENERGY METERING 1PHASE 24SSOP
CS5460A
5.5 Pulse-Rate Register
Address: 6
MSB
LSB
2
2
2
2
2
2
2
2
2
2
2
2
18
17
16
15
14
13
2
12
11
.....
2 1
0
-1
-2
-3
-4
2 -5
Default** = 32000.00Hz
The Pulse-Rate Register determines the frequency of the train of pulses output on the EOUT pin. Each EOUT
pulse represents a predetermined magnitude of real (billable) energy. The register’s smallest valid value is 2 -4
but can be in 2 -5 increments.
5.6 I,V,P,E Signed Output Register Results
Address: 7 - 10
MSB
LSB
-(2 0 )
2 -1
2 -2
2 -3
2 -4
2 -5
2 -6
2 -7
.....
2 -17
2 -18
2 -19
2 -20
2 -21
2 -22
2 -23
These signed registers contain the last value of the measured results of I, V, P, and E. The results are in the
range of -1.0 ? I, V, P, E ? 1.0. The value is represented in two's complement notation, with the binary point
place to the right of the MSB (which is the sign bit). I, V, P, and E are output results registers which contain
signed values. Note that the I, V, and P Registers are updated every conversion cycle, while the E Register is
only updated after each computation cycle. The numeric format of this register is two’s complement notation.
5.7 I RMS , V RMS Unsigned Output Register Results
Address: 11,12
MSB
LSB
2 -1
2 -2
2 -3
2 -4
2 -5
2 -6
2 -7
2 -8
.....
2 -18
2 -19
2 -20
2 -21
2 -22
2 -23
2 -24
These unsigned registers contain the last value of the calculated results of I RMS and V RMS . The results are in
the range of 0.0 ? I RMS ,V RMS ? 1.0. The value is represented in binary notation, with the binary point place to
the left of the MSB. I RMS and V RMS are output result registers which contain unsigned values.
5.8 Timebase Calibration Register
Address: 13
MSB
LSB
2 0
2 -1
2 -2
2 -3
2 -4
2 -5
2 -6
2 -7
.....
2 -17
2 -18
2 -19
2 -20
2 -21
2 -22
2 -23
Default** = 1.000
The Timebase Calibration Register is initialized to 1.0 on reset, allowing the device to function and perform com-
putations. The register can be loaded with the clock frequency error to compensate for a gain error caused by
the crystal/oscillator tolerance. The value is in the range 0.0 ?? TBC ? 2.0.
DS487F5
47
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