- 您现在的位置：买卖IC网 > Datasheet目录969 > CDK5581 (Cirrus Logic Inc)KIT BOARD FOR CDB5581 ADC Datasheet资料下载
参数资料
| 型号： | CDK5581 |
| 厂商： | Cirrus Logic Inc |
| 文件页数： | 24/32页 |
| 文件大小： | 0K |
| 描述： | KIT BOARD FOR CDB5581 ADC |
| 标准包装： | 1 |
| 系列： | CapturePLUS™II |
| ADC 的数量： | 1 |
| 位数： | 16 |
| 采样率（每秒）： | 200k |
| 数据接口： | 串行 |
| 输入范围： | ±2.048 V |
| 在以下条件下的电源（标准）： | 85mW @ 200kSPS |
| 工作温度： | -40°C ~ 85°C |
| 已用 IC / 零件： | CS5581 |
| 已供物品： | 2 个板，线缆，CD，电源 |
| 产品目录页面： | 756 (CN2011-ZH PDF) |
| 相关产品： | 598-1272-5-ND - IC ADC 16BIT 1CH 200KSPS 24SSOP |
| 其它名称： | 598-1574 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页当前第24页第25页第26页第27页第28页第29页第30页第31页第32页
3/25/08
14:34
CS5581
3.10 Serial Port
The serial port on the CS5581 can operate in two different modes: synchronous self clock (SSC) mode &
synchronous external clock (SEC) mode.
3.10.1 SSC Mode
If the SMODE pin is high (SMODE = VL), the serial port operates in the SSC (Synchronous Self Clock)
mode. In the SSC mode the port shifts out conversion data words with SCLK as an output. SCLK is gen-
erated inside the converter from MCLK. Data is output from the SDO (Serial Data Output) pin. If CS is
high, the SDO and SCLK pins will stay in a high-impedance state. If CS is low when RDY falls, the con-
version data word will be output from SDO MSB first. Data is output on the rising edge of SCLK and should
be latched into the external logic on the subsequent rising edge of SCLK. When all bits of the conversion
word are output from the port the RDY signal will return to high.
3.10.2 SEC Mode
If the SMODE pin is low (SMODE = VLR), the serial port operates in the SEC (Synchronous External
Clock mode). In this mode, the user usually monitors RDY. When RDY falls at t he end of a conversion,
the conversion data word is placed into the output data register in the serial port. CS is then activated low
to enable data output. Note that CS can be held low continuously if it is not necessary to have the SDO
output operate in the high impedance state. When CS is taken low (after RDY falls) the conversion data
word is then shifted out of the SDO pin by driving the SCLK pin from system logic external to the converter.
Data bits are advanced on rising edges of SCLK and latched by the subsequent rising edge of SCLK.
If CS is held low continuously, the RDY signal will fall at the end of a conversion and the conversion data
will be placed into the serial port. If the user starts a read, the user will maintain control over the serial port
until the port is empty. However, if SCLK is not toggled, the converter will overwrite the conversion data
at the completion of the next conversion. If CS is held low and no read is performed, RDY will rise just
prior to the end of the next conversion and then fall to signal that new data has been written into the serial
port.
3.11 Power Supplies & Grounding
The CS5581 can be configured to operate with its analog supply operating from 5V, or with its analog sup-
plies operating from ±2.5V. The digital interface supports digital logic operating from either 1.8V, 2.5V, or
3.3V.
Figure 6 on page 17 illustrates the device configured to operate from ±2.5V analog. Figure 7 on page 18
illustrates the device configured to operate from 5V analog.
To maximize converter performance, the analog ground and the logic ground for the converter should be
connected at the converter. In the dual analog supply configuration, the analog ground for the ±2.5V sup-
plies should be connected to the VLR pin at the converter with the converter placed entirely over the an-
alog ground plane.
In the single analog supply configuration (+5V), the ground for the +5V supply should be directly tied to
the VLR pin of the converter with the converter placed entirely over the analog ground plane. Refer to
24
DS796PP1
相关PDF资料 |
PDF描述 |
|---|---|
| CF1176-000 | SHIELD TERMINATOR |
| SMS4SE4K9 | 集管和线壳 4P QIKMATE PIN STRT PC BOARDMOUNT |
| CF6147-000 | CABLE TERMINATION |
| CF6153-000 | HEAT SHRINK TUBING |
| 22-56-6507 | 集管和线壳 CGrid SL Hsg Opt F D Hsg Opt F DR 50Ckt |
相关代理商/技术参数 |
参数描述 |
|---|---|
| CDK6 | 制造商:SPC Multicomp 功能描述:TERMINAL BLOCK 6MM 2DECK 制造商:SPC Multicomp 功能描述:TERMINAL BLOCK, 6MM, 2DECK |
| CDK7058 | 制造商:Renesas Electronics Corporation 功能描述:SUPPTOOL_RTE - Bulk |
| CDK8307 | 制造商:CADEKA 制造商全称:CADEKA 功能描述:12/13-bit, 20/40/50/65MSPS, Eight Channel, Ultra Low Power ADC with LVDS |
| CDK8307_1A | 制造商:CADEKA 制造商全称:CADEKA 功能描述:12/13-bit, 20/40/50/65/80MSPS, Eight Channel, Ultra Low Power ADC with LVDS |
| CDK8307AILP64 | 制造商:CADEKA 制造商全称:CADEKA 功能描述:12/13-bit, 20/40/50/65MSPS, Eight Channel, Ultra Low Power ADC with LVDS |
发布紧急采购，3分钟左右您将得到回复。