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参数资料
| 型号： | CDK5581 |
| 厂商： | Cirrus Logic Inc |
| 文件页数： | 25/32页 |
| 文件大小： | 0K |
| 描述： | KIT BOARD FOR CDB5581 ADC |
| 标准包装： | 1 |
| 系列： | CapturePLUS™II |
| ADC 的数量： | 1 |
| 位数： | 16 |
| 采样率（每秒）： | 200k |
| 数据接口： | 串行 |
| 输入范围： | ±2.048 V |
| 在以下条件下的电源（标准）： | 85mW @ 200kSPS |
| 工作温度： | -40°C ~ 85°C |
| 已用 IC / 零件： | CS5581 |
| 已供物品： | 2 个板，线缆，CD，电源 |
| 产品目录页面： | 756 (CN2011-ZH PDF) |
| 相关产品： | 598-1272-5-ND - IC ADC 16BIT 1CH 200KSPS 24SSOP |
| 其它名称： | 598-1574 |
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3/25/08
14:34
CS5581
3.12 Using the CS5581 in Multiplexing Applications
The CS5581 is a delta-sigma A/D converter. Delta-sigma converters use oversampling as means to
achieve high signal to noise. This means that once a conversion is started, the converter takes many sam-
ples to compute the resulting output word. The analog input for the signal to be converted must remain
active during the entire conversion until RDY falls.
The CS5581 can be used in multiplexing applications, but the system timing for changing the multiplexer
channel and for starting a new conversion will depend upon the multiplexer system architecture.
The simplest system is illustrated in Figure 21 . Any time the multiplexer is changed, the analog signal
presented to the converter must fully settle. After the signal has settled, the CONV signal is issued to the
converter to start a conversion. Being a delta-sigma converter, the signal must remain present at the input
of the converter until the conversion is completed. Once the conversion is completed, RDY falls. At this
time the multiplexer can be changed to the next channel and the data can be read from the serial port.
The CONV signal should be delayed until after the data is read and until the new analog signal has settled.
In this configuration, the throughput of the converter will be dictated by the settling time of the analog input
circuit and the conversion time of the converter. The conversion data can be read from the serial port after
the multiplexer is changed to the new channel while the analog input signal is settling.
CS5581
CH1
CH2
CH3
CH4
90
150pF
2k
4700pF
C0G
AIN
ACOM
Amplifier
Amplifier
CONV
RDY
Settling Time
Conversion Time
Settling Time
Advance
Mux
CH1
Throughput
CH2
Figure 21. Simple Multiplexing Scheme
A more complex multiplexing scheme can be used to increase the throughput of the converter is illustrated
in Figure 22 . In this circuit, two banks of multiplexers are used.
DS796PP1
25
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|---|---|
| CDK6 | 制造商:SPC Multicomp 功能描述:TERMINAL BLOCK 6MM 2DECK 制造商:SPC Multicomp 功能描述:TERMINAL BLOCK, 6MM, 2DECK |
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| CDK8307 | 制造商:CADEKA 制造商全称:CADEKA 功能描述:12/13-bit, 20/40/50/65MSPS, Eight Channel, Ultra Low Power ADC with LVDS |
| CDK8307_1A | 制造商:CADEKA 制造商全称:CADEKA 功能描述:12/13-bit, 20/40/50/65/80MSPS, Eight Channel, Ultra Low Power ADC with LVDS |
| CDK8307AILP64 | 制造商:CADEKA 制造商全称:CADEKA 功能描述:12/13-bit, 20/40/50/65MSPS, Eight Channel, Ultra Low Power ADC with LVDS |
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