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参数资料
| 型号： | CDK5581 |
| 厂商： | Cirrus Logic Inc |
| 文件页数： | 28/32页 |
| 文件大小： | 0K |
| 描述： | KIT BOARD FOR CDB5581 ADC |
| 标准包装： | 1 |
| 系列： | CapturePLUS™II |
| ADC 的数量： | 1 |
| 位数： | 16 |
| 采样率（每秒）： | 200k |
| 数据接口： | 串行 |
| 输入范围： | ±2.048 V |
| 在以下条件下的电源（标准）： | 85mW @ 200kSPS |
| 工作温度： | -40°C ~ 85°C |
| 已用 IC / 零件： | CS5581 |
| 已供物品： | 2 个板，线缆，CD，电源 |
| 产品目录页面： | 756 (CN2011-ZH PDF) |
| 相关产品： | 598-1272-5-ND - IC ADC 16BIT 1CH 200KSPS 24SSOP |
| 其它名称： | 598-1574 |
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4. PIN DESCRIPTIONS
3/26/08
10:50
CS5581
Chip Select
Factory Test
Serial Mode Select
Analog Input
Analog Return
Negative Power 1
Positive Power 1
Buffer Enable
Voltage Reference Input
Voltage Reference Input
Bipolar/Unipolar Select
Logic Interface Return 2
CS
TST
SMODE
AIN
ACOM
V1-
V1+
BUFEN
VREF+
VREF-
BP/UP
VLR2
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
RDY
SCLK
SDO
VL
VLR
MCLK
V2-
V2+
DCR
CONV
VLR3
RST
Ready
Serial Clock Input/Output
Serial Data Output
Logic Interface Power
Logic Interface Return
Master Clock
Negative Voltage 2
Positive Voltage 2
Digital Core Regulator
Convert
Logic Interface Return 3
Reset
CS – Chip Select, Pin 1
The Chip Select pin allows an external device to access the serial port. When held high, the
SDO output will be held in a high-impedance output state.
TST – Factory Test, Pin 2
For factory use only. Connect to VLR.
SMODE – Serial Mode Select, Pin 3
The serial interface mode pin (SMODE) dictates whether the serial port behaves as a master or
slave interface. If SMODE is tied high (to VL), the port will operate in the Synchronous
Self-Clocking (SSC) mode. In SSC mode, the port acts as a master in which the converter out-
puts both the SDO and SCLK signals. If SMODE is tied low (to VLR), the port will operate in the
Synchronous External Clocking (SEC) mode. In SEC mode, the port acts as a slave in which
the external logic or microcontroller generates the SCLK used to output the conversion data
word from the SDO pin.
AIN – Analog Input, Pin 4
AIN is the single-ended input.
ACOM – Analog Return, Pin 5
ACOM is the analog return for the input signal.
V1- – Negative Power 1, Pin 6
The V1- and V2- pins provide a negative supply voltage to the core circuitry of the chip. These
two pins should be decoupled as shown in the application block diagrams. V1- and V2- should
be supplied from the same source voltage. For single-supply operation, these two voltages are
nominally 0 V (Ground). For dual-supply, operation they are nominally -2.5 V.
V1+ – Positive Power 1, Pin 7
The V1+ and V2+ pins provide a positive supply voltage to the core circuitry of the chip. These
two pins should be decoupled as shown in the application block diagrams. V1+ and V2+ should
be supplied from the same source voltage. For single-supply operation, these two voltages are
nominally +5 V. For dual-supply operation, they are nominally +2.5 V.
BUFEN – Buffer Enable, Pin 8
Buffers on input pins AIN and ACOM are enabled if BUFEN is connected to V1+ and disabled if
connected to V1-.
VREF+, VREF- – Voltage Reference Input, Pins 9, 10
A differential voltage reference input on these pins functions as the voltage reference for the
converter. The voltage between these pins can range between 2.4 volts and 4.2 volts, with
4.096 volts being the nominal reference voltage value.
28
DS796PP1
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