参数资料
型号: CS5301GDWR32G
厂商: ON Semiconductor
文件页数: 13/19页
文件大小: 0K
描述: IC REG CTRLR BUCK PWM 32-SOIC
产品变化通告: Product Obsolescence 24/Jan/2011
标准包装: 1
PWM 型: 电流/电压模式,V²?
输出数: 1
频率 - 最大: 1MHz
电源电压: 4.7 V ~ 20 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: 0°C ~ 70°C
封装/外壳: 32-SOIC(0.295",7.50mm 宽)
包装: 剪切带 (CT)
其它名称: CS5301GDWR32GOSCT
CS5301
considered when setting the I LIM threshold. If a more
SWNODE
V FB (V OUT )
CSA Out
COMP ? Offset
CSA Out + V FB
T1 T2
Figure 10. Open Loop Operation
Inductive Current Sensing
For lossless sensing, current can be sensed across the
inductor as shown in Figure 11. In the diagram L is the output
inductance and R L is the inherent inductor resistance. To
compensate the current sense signal the values of R1 and C1
are chosen so that L/R L = R1 × C1. If this criteria is met the
current sense signal will be the same shape as the inductor
current, the voltage signal at CS x will represent the
instantaneous value of inductor current and the circuit can be
analyzed as if a sense resistor of value R L was used as a sense
resistor (R S ).
accurate current sense is required than inductive sensing can
provide, current can be sensed through a resistor as shown
in Figure 9.
Current Sharing Accuracy
PCB traces that carry inductor current can be used as part
of the current sense resistance depending on where the
current sense signal is picked off. For accurate current
sharing, the current sense inputs should sense the current at
the same point for each phase and the connection to the
CS REF should be made so that no phase is favored. (In some
cases, especially with inductive sensing, resistance of the
pcb can be useful for increasing the current sense
resistance.) The total current sense resistance used for
calculations must include any pcb trace between the CS x
inputs and the CS REF input that carries inductor current.
Current Sense Amplifier Input Mismatch and the value of
the current sense element will determine the accuracy of
current sharing between phases. The worst case Current
Sense Amplifier Input Mismatch is 5.0 mV and will
typically be within 3.0 mV. The difference in peak currents
between phases will be the CSA Input Mismatch divided by
the current sense resistance. If all current sense elements are
of equal resistance a 3.0 mV mismatch with a 2.0 m W sense
resistance will produce a 1.5 A difference in current between
phases.
Operation at > 50% Duty Cycle
For operation at duty cycles above 50% Enhanced V 2 will
SWNODE
V OUT
L
R L
R1
C1
CS X
CS REF
V FB
+
CSA
OFFSET
+
+
+
+
PWM
COMP
exhibit subharmonic oscillation unless a compensation
ramp is added to each phase. A circuit like the one on the left
side of Figure 12 can be added to each current sense network
to implement slope compensation. The value of R1 can be
varied to adjust the ramp size.
Switch Node
Gate(L)X
DAC OUT
COMP
E.A.
+
3.0 k
R1
25 k
Figure 11. Lossless Inductive Current Sensing with
Enhanced V 2
When choosing or designing inductors for use with
inductive sensing tolerances and temperature effects should
be considered. Cores with a low permeability material or a
MMBT2222LT1
1.0 nF
0.1 m F
.01 m F
CS X
CS REF
large gap will usually have minimal inductance change with
temperature and load. Copper magnet wire has a
temperature coefficient of 0.39% per ° C. The increase in
Slope Comp
Circuit
Existing Current
Sense Circuit
winding resistance at higher temperatures should be
Figure 12. External Slope Compensation Circuit
http://onsemi.com
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