参数资料
| 型号： | CS5301GDWR32G |
| 厂商： | ON Semiconductor |
| 文件页数： | 15/19页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR BUCK PWM 32-SOIC |
| 产品变化通告： | Product Obsolescence 24/Jan/2011 |
| 标准包装： | 1 |
| PWM 型： | 电流/电压模式，V²? |
| 输出数： | 1 |
| 频率 - 最大： | 1MHz |
| 电源电压： | 4.7 V ~ 20 V |
| 降压： | 是 |
| 升压： | 无 |
| 回扫： | 无 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 无 |
| 工作温度： | 0°C ~ 70°C |
| 封装/外壳： | 32-SOIC（0.295"，7.50mm 宽） |
| 包装： | 剪切带 (CT) |
| 其它名称： | CS5301GDWR32GOSCT |
CS5301
UVLO
The CS5301 has undervoltage lockout functions connected
to two pins. One intended for the logic and low?side drivers
with a 4.5 V turn?on threshold is connected to the V CCL pin.
A second for the high side drivers has a 3.5 V threshold and
is connected to the V CCH12 pin.
The UVLO threshold for the high side drivers was chosen
at a low value to allow for flexibility in the part. In many
applications this function will be disabled or will only check
that the applicable supply is on ? not that is at a high enough
voltage to run the converter.
For the 12 VIN converter (see Figure 1) the UVLO pin for
the high side driver is pulled up by the 5.0 V supply (through
two diode drops) and the function is not used. The diode
between the COMP pin and the 12 V supply holds the COMP
pin near GND and prevents start?up while the 12 V supply
is off. In an application where a higher UVLO threshold is
necessary a circuit like the one in Figure 15 will lock out the
converter until the 12 V supply exceeds 8.0 V.
VID Codes and Power Good
The internal VID and DAC OUT levels are set up so that the
reference for the control loop is nominally 125 mV below
the VID code (see the block diagram). The nominal lower
Power Good threshold is 2.5% below the DAC OUT level.
The nominal upper Power Good threshold is fixed at 2.0 V
for all VID codes. This scheme is intended to select the VID
level as the maximum output voltage and the DAC OUT level
as the minimum output voltage.
TRANSIENT RESPONSE AND ADAPTIVE
POSITIONING
For applications with fast transient currents the output
filter is frequently sized larger than ripple currents require in
order to reduce voltage excursions during transients.
Adaptive voltage positioning can reduce peak?peak output
voltage deviations during load transients and allow for a
smaller output filter. The output voltage can be set higher at
light loads to reduce output voltage sag when the load
current is stepped up and set lower during heavy loads to
reduce overshoot when the load current is stepped up. For
low current applications a droop resistor can provide fast
accurate adaptive positioning. However, at high currents the
loss in a droop resistor becomes excessive. For example; in
a 50 A converter a 1.0 m W resistor to provide a 50 mV
change in output voltage between no load and full load
would dissipate 2.5 Watts.
Lossless adaptive positioning is an alternative to using a
droop resistor, but must respond quickly to changes in load
current. Figure 14 shows how adaptive positioning works.
The waveform labeled normal shows a converter without
adaptive positioning. On the left, the output voltage sags
when the output current is stepped up and later overshoots
when current is stepped back down. With fast (ideal)
adaptive positioning the peak to peak excursions are cut in
half. In the slow adaptive positioning waveform the output
voltage is not repositioned quickly enough after current is
stepped up and the upper limit is exceeded.
Normal
Fast Adaptive Positioning
Slow Adaptive Positioning
Limits
Figure 14. Adaptive Positioning
The CS5301 uses two methods to provide fast and
accurate adaptive positioning. For low frequency
positioning the VFB and VDRP pins are used to adjust the
output voltage with varying load currents. For high
frequency positioning, the current sense input pins can be
used to control the power stage output impedance. The
transition between fast and slow positioning is adjusted by
the error amp compensation.
The CS5301 can be configured to adjust the output
voltage based on the output current of the converter, as
shown in Figure 1.
To set the no?load positioning, a resistor (R9) is placed
between the output voltage and V FB pin. The V FB bias
current will develop a voltage across the resistor to decrease
the output voltage. The V FB bias current is dependent on the
value of R ROSC , as shown in Figure 4.
During no load conditions the V DRP pin is at the same
voltage as the V FB pin, so none of the V FB bias current flows
through the V DRP resistor (R8). When output current
increases the V DRP pin increases proportionally and the
V DRP pin current offsets the V FB bias current and causes the
output voltage to further decrease.
The V FB and V DRP pins take care of the slower and DC
voltage positioning. The first few m s are controlled primarily
by the ESR and ESL of the output filter. The transition
between fast and slow positioning is controlled by the ramp
size and the error amp compensation. If the ramp size is too
large or the error amp too slow there will be a long transition
to the final voltage after a transient. This will be most
apparent with lower capacitance output filters.
Note: Large levels of adaptive positioning can cause pulse
width jitter.
Error Amp Compensation
The transconductance error amplifier can be configured to
provide both a slow soft?start and a fast transient response.
C4 in Figure 1 controls soft?start. A 0.1 m F capacitor with
the 30 m A error amplifier output capability will allow the
output to ramp up at 0.3 V/ms or 1.5 V in 5.0 ms.
R10 is connected in series with C4 to allow the error
amplifier to slew quickly over a narrow range during load
transients. Here the 30 m A error amplifier output capability
http://onsemi.com
15
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