参数资料
| 型号： | CS5301GDWR32G |
| 厂商： | ON Semiconductor |
| 文件页数： | 6/19页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR BUCK PWM 32-SOIC |
| 产品变化通告： | Product Obsolescence 24/Jan/2011 |
| 标准包装： | 1 |
| PWM 型： | 电流/电压模式，V²? |
| 输出数： | 1 |
| 频率 - 最大： | 1MHz |
| 电源电压： | 4.7 V ~ 20 V |
| 降压： | 是 |
| 升压： | 无 |
| 回扫： | 无 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 无 |
| 工作温度： | 0°C ~ 70°C |
| 封装/外壳： | 32-SOIC（0.295"，7.50mm 宽） |
| 包装： | 剪切带 (CT) |
| 其它名称： | CS5301GDWR32GOSCT |
CS5301
ELECTRICAL CHARACTERISTICS (0 ° C < T A < 70 ° C; 0 ° C < T J < 125 ° C; 4.7 V < V CCL < 14 V; 8.0 V < V CCH < 20 V;
C GATE(H) = 3.3 nF, C GATE(L) = 3.3 nF, R ROSC = 53.6 k, C COMP = 0.1 m F, C REF = 0.1 m F, DAC Code 10000, C VCC = 1.0 m F, I LIM ≥ 1.0 V;
unless otherwise specified.)
Characteristic
Test Conditions
Min
Typ
Max
Unit
Voltage Feedback Error Amplifier
V FB Bias Current, (Note 2)
COMP Source Current
0.9 V < V FB < 1.8 V
COMP = 0.5 V to 2.0 V;
5.5
15
6.0
30
6.5
60
m A
m A
V FB = 1.6 V; DAC = 00000
COMP Sink Current
COMP = 0.5 V to 2.0 V;
15
30
60
m A
V FB = 1.8 V; DAC = 00000
COMP Discharge Threshold Voltage
Transconductance
Output Impedance
Open Loop DC Gain
Unity Gain Bandwidth
PSRR @ 1.0 kHz
COMP Max Voltage
?
?10 m A < I COMP < +10 m A
?
Note 3.
0.01 m F COMP Capacitor
?
V FB = 1.65 V COMP Open;
0.20
?
?
60
?
?
2.4
0.27
32
2.5
90
400
70
2.7
0.34
?
?
?
?
?
?
V
mmho
M W
dB
kHz
dB
V
DAC = 00000
COMP Min Voltage
V FB = 1.8 V COMP Open;
?
0.1
0.2
V
DAC = 00000
Hiccup Latch Discharge Current
?
2
5.0
10
m A
PWM Comparators
Minimum Pulse Width
Measured from CSx to GATE(H),
?
350
515
ns
V(V FB ) = V(CS REF ) = 0 V,
V(COMP) = 0.5 V, 60 mV step
applied between V CSX and V CREF
Channel Startup Offset
V(CS1) = V(CS2) = V(CS3) =
0.3
0.4
0.5
V
V(V FB ) = V(CS REF ) = 0 V;
Measure V(COMP) when
GATE1(H), 2(H), 3(H) switch high
GATE(H) and GATE(L)
High Voltage (AC)
(Note 3). Measure V CCLX ?
?
0
1.0
V
GATE(L)
or V CCHX ? GATE(H)
Low Voltage (AC)
(Note 3). Measure GATE(L)
?
0
0.5
V
or GATE(H)
Rise Time GATE(H)x
Rise Time GATE(L)x
Fall Time GATE(H)x
Fall Time GATE(L)x
GATE(H) to GATE(L) Delay
GATE(L) to GATE(H) Delay
GATE Pull?down
1.0 V < GATE < 8.0 V; V CCHX = 10 V
1.0 V < GATE < 8.0 V; V CCLX = 10 V
8.0 V > GATE > 1.0 V; V CCHX = 10 V
8.0 V > GATE > 1.0 V; V CCLX = 10 V
GATE(H) < 2.0 V, GATE(L) > 2.0 V
GATE(L) < 2.0 V, GATE(H) > 2.0 V
Force 100 m A into GATE Driver
?
?
?
?
30
30
?
35
35
35
35
65
65
1.2
80
80
80
80
110
110
1.6
ns
ns
ns
ns
ns
ns
V
with V CCHX = V CCLX = 2.0 V
2. The V FB Bias Current changes with the value of R ROSC per Figure 4.
3. Guaranteed by design. Not tested in production.
http://onsemi.com
6
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