参数资料
| 型号： | CS5301GDWR32G |
| 厂商： | ON Semiconductor |
| 文件页数： | 9/19页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR BUCK PWM 32-SOIC |
| 产品变化通告： | Product Obsolescence 24/Jan/2011 |
| 标准包装： | 1 |
| PWM 型： | 电流/电压模式，V²? |
| 输出数： | 1 |
| 频率 - 最大： | 1MHz |
| 电源电压： | 4.7 V ~ 20 V |
| 降压： | 是 |
| 升压： | 无 |
| 回扫： | 无 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 无 |
| 工作温度： | 0°C ~ 70°C |
| 封装/外壳： | 32-SOIC（0.295"，7.50mm 宽） |
| 包装： | 剪切带 (CT) |
| 其它名称： | CS5301GDWR32GOSCT |
CS5301
PACKAGE PIN DESCRIPTION
PACKAGE PIN #
1
2
3
4?6
7
8
9?13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
PIN SYMBOL
COMP
V FB
V DRP
CS1?CS3
CS REF
PWRGD
V ID4 ?V ID0
PWRGDS
I LIM
REF
LGND
V CCH3
Gate(H)3
GND3
Gate(L)3
V CCL23
Gate(L)2
GND2
Gate(H)2
V CCH12
Gate(H)1
GND1
Gate(L)1
V CCL1
V CCL
R OSC
FUNCTION
Output of the error amplifier and input for the PWM comparators.
Voltage Feedback Pin. To use Adaptive Voltage Positioning (AVP) select an
offset voltage at light load and connect a resistor between V FB and V OUT . The
input bias current of the V FB pin and the resistor value determine output voltage
offset for zero output current. Short V FB to V OUT for no AVP.
Current sense output for AVP. The offset of this pin above the DAC voltage is
proportional to the output current. Connect a resistor from this pin to V FB to set
amount AVP or leave this pin open for no AVP.
Current sense inputs. Connect current sense network for the corresponding
phase to each input.
Reference for current sense amplifiers. To balance input offset voltages between
the inverting and noninverting inputs of the Current Sense Amplifiers, connect a
resistor between CS REF and the output voltage. The value should be 1/3 of the
value of the resistors connected to the CSx pins.
Power Good Output. Open collector output goes low when CS REF is out of
regulation.
Voltage ID DAC inputs. These pins are internally pulled up to 3.3 V if left open.
Power Good Sense. Connect to Output.
Sets threshold for current limit. Connect to reference through a resistive divider.
Reference output. Decouple with 0.1 m F to LGND.
Return for internal control circuits and IC substrate connection.
Power for GATE(H)3.
High side driver #3.
Return for #3 drivers.
Low side driver #3.
Power for GATE(L)2 and GATE(L)3.
Low side driver #2.
Return for #2 driver.
High side driver #2.
Power for GATE(H)1 and GATE(H)2. UVLO Sense for High Side Driver supply
connects to this pin.
High side driver #1.
Return #1 drivers.
Low side driver #1.
Power for GATE(L)1.
Power for internal control circuits and UVLO Sense for Logic.
A resistor from this pin to ground sets operating frequency and V FB bias current.
http://onsemi.com
9
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