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参数资料
| 型号： | CY39050V208-125NTXI |
| 厂商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分类： | PLD |
| 英文描述： | LOADABLE PLD, 10 ns, PQFP208 |
| 封装： | 28 X 28 MM, 0.50 MM PITCH, LEAD FREE, PLASTIC, EQFP-208 |
| 文件页数： | 1/86页 |
| 文件大小： | 2802K |
| 代理商： | CY39050V208-125NTXI |
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CPLDs at FPGA Densities
Delta39K ISR
CPLD Family
Cypress Semiconductor Corporation
3901 North First Street
San Jose
CA 95134
408-943-2600
Document #: 38-03039 Rev. *I
Revised March 11, 2005
Features
High density
— 30K to 200K usable gates
— 512 to 3072 macrocells
— 136 to 428 maximum I/O pins
— Twelve dedicated inputs including four clock pins,
four global I/O control signal pins and four JTAG
interface pins for boundary scan and reconfig-
urability
Embedded memory
— 80K to 480K bits embedded SRAM
16K to 96K bits of (dual-port) channel memory
High speed – 233-MHz in-system operation
AnyVolt interface
— 3.3V, 2.5V,1.8V, and 1.5V I/O capability
Low-power operation
— 0.18-mm six-layer metal SRAM-based logic process
— Full-CMOS implementation of product term array
— Standby current as low as 5mA
Simple timing model
— No penalty for using full 16 product terms/macrocell
— No delay for single product term steering or sharing
Flexible clocking
— Spread Aware PLL drives all four clock networks
Allows 0.6% spread spectrum input clocks
Several multiply, divide and phase shift options
— Four synchronous clock networks per device
— Locally generated product term clock
— Clock polarity control at each register
Carry-chain logic for fast and efficient arithmetic opera-
tions
Multiple I/O standards supported
— LVCMOS (3.3/3.0/2.5/1.8V), LVTTL, 3.3V PCI, SSTL2
(I-II), SSTL3 (I-II), HSTL (I-IV), and GTL+
Compatible with NOBL, ZBT, and QDR SRAMs
Programmable slew rate control on each I/O pin
User-programmable Bus Hold capability on each I/O pin
Fully 3.3V PCI-compliant (to 66-MHz 64-bit PCI spec,
rev. 2.2)
CompactPCI hot swap ready
Multiple package/pinout offering across all densities
— 208 to 676 pins in PQFP, BGA, and FBGA packages
— Simplifies design migration across density
— Self-Boot solution in BGA and FBGA packages
— Lead (Pb)-free packages available.
In-System Reprogrammable (ISR)
— JTAG-compliant on-board programming
— Design changes do not cause pinout changes
IEEE1149.1 JTAG boundary scan
Development Software
Warp
— IEEE 1076/1164 VHDL or IEEE 1364 Verilog context
sensitive editing
— Active-HDL FSM graphical finite state machine editor
— Active-HDL SIM post-synthesis timing simulator
— Architecture Explorer for detailed design analysis
— Static Timing Analyzer for critical path analysis
— Available on Windows 95/98/2000/XP and
Windows NT for $99
— Supports all Cypress programmable logic products
Delta39K ISR CPLD Family Members
Device
Typical
Gates[1]
Macrocells
Cluster
memory
(Kbits)
Channel
memory
(Kbits)
Maximum
I/O Pins
fMAX2
(MHz)
Speed-tPD
Pin-to-Pin
(ns)
Standby ICC[2]
TA = 25°C
3.3/2.5V
39K30
16K – 48K
512
64
16
174
233
7.2
5 mA
39K50
23K – 72K
768
96
24
218
233
7.2
5 mA
39K100
46K – 144K
1536
192
48
302
222
7.5
10 mA
39K200
92K – 288K
3072
384
96
428
181
8.5
20 mA
Notes:
1.
Upper limit of typical gates is calculated by assuming only 10% of the channel memory is used.
2.
Standby ICC values are with PLL not utilized, no output load and stable inputs.
相关PDF资料 |
PDF描述 |
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| CY39050V208-233NTXC | LOADABLE PLD, 7.2 ns, PQFP208 |
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| CY39050V208-83NTXI | LOADABLE PLD, 15 ns, PQFP208 |
| CY39200V208-181NTXC | LOADABLE PLD, 8.5 ns, PQFP208 |
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相关代理商/技术参数 |
参数描述 |
|---|---|
| CY39050V208-181BBC | 制造商:CYPRESS 制造商全称:Cypress Semiconductor 功能描述:CPLDs at FPGA Densities |
| CY39050V208-181BBI | 制造商:CYPRESS 制造商全称:Cypress Semiconductor 功能描述:CPLDs at FPGA Densities |
| CY39050V208-181BGC | 制造商:CYPRESS 制造商全称:Cypress Semiconductor 功能描述:CPLDs at FPGA Densities |
| CY39050V208-181BGI | 制造商:CYPRESS 制造商全称:Cypress Semiconductor 功能描述:CPLDs at FPGA Densities |
| CY39050V208-181MBC | 制造商:CYPRESS 制造商全称:Cypress Semiconductor 功能描述:CPLDs at FPGA Densities |
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