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参数资料
| 型号： | CY39050V208-125NTXI |
| 厂商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分类： | PLD |
| 英文描述： | LOADABLE PLD, 10 ns, PQFP208 |
| 封装： | 28 X 28 MM, 0.50 MM PITCH, LEAD FREE, PLASTIC, EQFP-208 |
| 文件页数： | 84/86页 |
| 文件大小： | 2802K |
| 代理商： | CY39050V208-125NTXI |
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Delta39K ISR
CPLD Family
Document #: 38-03039 Rev. *I
Page 85 of 86
Document History Page=
Document Title: Delta39K ISR CPLD Family CPLDs at FPGA Densities
Document Number: 38-03039
REV.
ECN NO.
Issue
Date
Orig. of
Change
Description of Change
**
106503
05/30/01
SZV
Change from Spec #: 38-00830 to 38-03039
*A
107625
07/11/01
RN
Deleted 39K15 device and the associated -250-MHz bin specs
Deleted 144FBGA package and associated part numbers
Changed ESD spec from “MIL-STD-883” to “JEDEC EIA/JESD22-A114-A”
Changed the Prime bin for 39K50 and 39K30 from “MHz” to “233 MHz”
Changed the part ordering information accordingly
Updated the -233-MHz timing specs to match modified timing specs achieved by
design (main affected params: tPD, tMCCO, tIOS, tSCS, tSCS2, fMAX2, tCLMAA,
tCLMCYC2, tCHMCYC2, tCHMCLK)
Updated I/O standard Timing Delay Specs and changed the default I/O standard
from 3.3V PCI to LVCMOS
Added paragraph about Delta39K being CompactPCI hot swap Ready
Added X8 mode in the PLL description
Added Standby ICC spec
Updated the recommended boot PROM for 39K165/200 to be CY3LV002 instead
of CY3LV020
*B
109681
11/16/01
RN
Updated Delta39K family offering
Modified PLL timing parameters tDWSA, tDWOSA, tMCCJ, and tLOCK. Added tINDUTY
parameter
Deleted exception to CompactPCI Hot Swap compliance regarding “PCI
buffers....”
Added reference to app note “Hot Socketing Delta39K”
Revised CompactPCI Hot Swap Specification R1.0 to be R2.0
*C
112376
12/21/01
RN
Combined with spec# 38-03040
*D
112946
04/04/02
RN
Updated pin tables for 39K30 (208PQFP, 256FBGA)
Updated pin tables for 39K50 (208PQFP, 256/484FBGA, 388BGA)
Added X3, X5, X6, X16 multiplication modes to Spread Aware PLL
Added PLL parameters (fPLLVCO, PSAPLLI, fMPPLI)
Added and updated Storage Temperature for 39K200-208EQFP
Changed the Icc0 spec for 39K165 and 39K200
Updated tCLZ, tCHMCYC2 parameter Values for -233 MHz bin
Updated Input and Output Standard Timing Delay Adjustment table
Removed Self Boot Industrial parts from the offering
Removed Delta39K165Z (1.8V) from the offering
Removed 144-FBGA package offering
Added self-boot Flash Memory endurance and data retention data
Added Family, Package, and Density Migration section
Added note 20 to 484/676 FBGA pin table to identify slow 39K165 IOs
*E
117518
10/04/02
OOR
Changed data sheet status from Preliminary to Final
Added note 7 to DC Characteristics
*F
121063
11/06/02
DSG
Updated spec 51-85103 (MG388 package drawing) to rev. *C
*G
122543
12/10/02
RN
Changed the definition of following pins on CY39030 -256FBGA package:
Pin A10: From IO/Vref7 to IO/Vref6
Pin B7: From IO/Vref6 to VCC
Added Table to identify Bank Location of Global Clock and Global Control Pins
*H
128684
08/04/03
OOR
Removed all “Z” parts (1.8V)
Referenced EEPROM to ATMEL part number
相关PDF资料 |
PDF描述 |
|---|---|
| CY39050V208-233NTXC | LOADABLE PLD, 7.2 ns, PQFP208 |
| CY39050V208-83NTXC | LOADABLE PLD, 15 ns, PQFP208 |
| CY39050V208-83NTXI | LOADABLE PLD, 15 ns, PQFP208 |
| CY39200V208-181NTXC | LOADABLE PLD, 8.5 ns, PQFP208 |
| CY39200V208-83NTXC | LOADABLE PLD, 15 ns, PQFP208 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| CY39050V208-181BBC | 制造商:CYPRESS 制造商全称:Cypress Semiconductor 功能描述:CPLDs at FPGA Densities |
| CY39050V208-181BBI | 制造商:CYPRESS 制造商全称:Cypress Semiconductor 功能描述:CPLDs at FPGA Densities |
| CY39050V208-181BGC | 制造商:CYPRESS 制造商全称:Cypress Semiconductor 功能描述:CPLDs at FPGA Densities |
| CY39050V208-181BGI | 制造商:CYPRESS 制造商全称:Cypress Semiconductor 功能描述:CPLDs at FPGA Densities |
| CY39050V208-181MBC | 制造商:CYPRESS 制造商全称:Cypress Semiconductor 功能描述:CPLDs at FPGA Densities |
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