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参数资料
| 型号： | CY39050V208-125NTXI |
| 厂商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分类： | PLD |
| 英文描述： | LOADABLE PLD, 10 ns, PQFP208 |
| 封装： | 28 X 28 MM, 0.50 MM PITCH, LEAD FREE, PLASTIC, EQFP-208 |
| 文件页数： | 13/86页 |
| 文件大小： | 2802K |
| 代理商： | CY39050V208-125NTXI |
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Delta39K ISR
CPLD Family
Document #: 38-03039 Rev. *I
Page 20 of 86
tMACCLMS2
Macrocell clock to cluster memory output clock in the same cluster
Internal Parameters
tCLMCLAA
Asynchronous cluster memory access time from input of cluster memory to output of cluster memory
Channel Memory Timing Parameter Descriptions Over the Operating Range
Parameter
Description
Dual Port Asynchronous Mode Parameters
tCHMAA
Channel memory access time. Delay from address change to Read data out
tCHMPWE
Write enable pulse width
tCHMSA
Address set-up to the beginning of Write enable with both signals from the same I/O block
tCHMHA
Address hold after the end of Write enable with both signals from the same I/O block
tCHMSD
Data set-up to the end of Write enable
tCHMHD
Data hold after the end of Write enable
tCHMBA
Channel memory asynchronous dual port address match (busy access time)
Dual Port Synchronous Mode Parameters
tCHMCYC1
Clock cycle time for flow through Read and Write operations (from macrocell register through channel
memory back to a macrocell register in the same cluster)
tCHMCYC2
Clock cycle time for pipelined Read and Write operations (from channel memory input register through the
memory to channel memory output register)
tCHMS
Address, data, and WE set-up time of pin inputs, relative to a global clock
tCHMH
Address, data, and WE hold time of pin inputs, relative to a global clock
tCHMDV1
Global clock to data valid on output pins for flow through data
tCHMDV2
Global clock to data valid on output pins for pipelined data.
tCHMBDV
Channel memory synchronous dual-port address match (busy, clock to data valid)
tCHMMACS1
Channel memory input clock to macrocell clock in the same cluster
tCHMMACS2
Channel memory output clock to macrocell clock in the same cluster
tMACCHMS1
Macrocell clock to channel memory input clock in the same cluster
tMACCHMS2
Macrocell clock to channel memory output clock in the same cluster
Synchronous FIFO Data Parameters
tCHMCLK
Read and Write minimum clock cycle time
tCHMFS
Data, Read enable, and Write enable set-up time relative to pin inputs
tCHMFH
Data, Read enable, and Write enable hold time relative to pin inputs
tCHMFRDV
Data access time to output pins from rising edge of Read clock (Read clock to data valid)
tCHMMACS
Channel memory FIFO Read clock to macrocell clock for Read data
tMACCHMS
Macrocell clock to channel memory FIFO Write clock for Write data
Synchronous FIFO Flag Parameters
tCHMFO
Read or Write clock to respective flag output at output pins
tCHMMACF
Read or Write clock to macrocell clock with FIFO flag
tCHMFRS
Master Reset Pulse Width
tCHMFRSR
Master Reset Recovery Time
tCHMFRSF
Master Reset to Flag and Data Output Time
tCHMSKEW1
Read/Write Clock Skew Time for Full Flag
tCHMSKEW2
Read/Write Clock Skew Time for Empty Flag
tCHMSKEW3
Read/Write Clock Skew Time for Boundary Flags
Cluster Memory Timing Parameter Descriptions Over the Operating Range (continued)
Parameter
Description
相关PDF资料 |
PDF描述 |
|---|---|
| CY39050V208-233NTXC | LOADABLE PLD, 7.2 ns, PQFP208 |
| CY39050V208-83NTXC | LOADABLE PLD, 15 ns, PQFP208 |
| CY39050V208-83NTXI | LOADABLE PLD, 15 ns, PQFP208 |
| CY39200V208-181NTXC | LOADABLE PLD, 8.5 ns, PQFP208 |
| CY39200V208-83NTXC | LOADABLE PLD, 15 ns, PQFP208 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| CY39050V208-181BBC | 制造商:CYPRESS 制造商全称:Cypress Semiconductor 功能描述:CPLDs at FPGA Densities |
| CY39050V208-181BBI | 制造商:CYPRESS 制造商全称:Cypress Semiconductor 功能描述:CPLDs at FPGA Densities |
| CY39050V208-181BGC | 制造商:CYPRESS 制造商全称:Cypress Semiconductor 功能描述:CPLDs at FPGA Densities |
| CY39050V208-181BGI | 制造商:CYPRESS 制造商全称:Cypress Semiconductor 功能描述:CPLDs at FPGA Densities |
| CY39050V208-181MBC | 制造商:CYPRESS 制造商全称:Cypress Semiconductor 功能描述:CPLDs at FPGA Densities |
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