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参数资料
型号： CY39050V208-222NTC
厂商： CYPRESS SEMICONDUCTOR CORP
元件分类： PLD
英文描述： LOADABLE PLD, 7 ns, PQFP208
封装： THERMALLY ENHANCED, QFP-208
文件页数： 1/57页
文件大小： 1166K
代理商： CY39050V208-222NTC
CPLDs at FPGA Densities
Delta39K ISR
CPLD Family
PRELIMINARY
Cypress Semiconductor Corporation
3901 North First Street
San Jose
CA 95134
408-943-2600
Document #: 38-03039 Rev. **
Revised April 4, 2001
Features
High density
— 15K to 350K usable gates
— 256 to 5376 macrocells
— 92 to 520 maximum I/O pins
— 12 Dedicated Inputs including 4 clock pins, 4 global
control signal pins and 4 JTAG interface pins for
reconfigurability
Embedded Memory
— 40K to 840K bits embedded SRAM
32K to 672K bits of (single port) Cluster memory
8K to 168K bits of (dual port) Channel memory
High speed - 250-MHz in-system operation
AnyVolt interface
— 3.3V, 2.5V and 1.8V VCC versions available
— 3.3V, 2.5V and 1.8V I/O capability on all versions
Low Power Operation
— 0.18-
m 6-layer metal SRAM-based logic process
— Full-CMOS implementation of product term array
— Standby current as low as 100
A at 1.8V V
CC
Simple timing model
— No penalty for using full 16 product terms / macrocell
— No delay for single product term steering or sharing
Flexible clocking
— 4 synchronous clocks per device
— 1 spread-aware PLL drives all 4 clock networks
— Locally generated Product Term clock
— Clock polarity control at each register
Carry-chain logic for fast and efficient arithmetic opera-
tions
Multiple I/O standards supported
— LVCMOS (3.3/3.0/2.5/1.8V), LVTTL, 3.3V PCI, SSTL2
(I-II), SSTL3 (I-II), HSTL (I-IV), and GTL+
Compatible with NOBL, ZBT, and QDR SRAMs
Programmable slew rate control on each I/O pin
User-Programmable Bus Hold capability on each I/O pin
Fully PCI compliant (to 66 MHz 64-bit PCI spec rev2.2)
Compact PCI hot swap compatible
Multiple package/pinout offering across all densities
— 144 to 676 pins in PQFP, BGA and FBGA packages
— Same pinout for 3.3V/2.5V and 1.8V devices
— Simplifies design migration across density
— Self-Boot solution in BGA and FBGA packages
In-System Reprogrammable (ISR)
— JTAG-compliant on-board programming
— Design changes don’t cause pinout changes
IEEE1149.1 JTAG boundary scan
Development Software
Warp
— IEEE 1076/1164 VHDL or IEEE 1364 Verilog context
sensitive editing.
— Active-HDL FSM graphical finite state machine editor
— Active-HDL SIM post-synthesis timing simulator
— Architecture Explorer for detailed design analysis
— Static Timing Analyzer for critical path analysis
— Available on Windows 95, 98 & NT for $99
— Supports all Cypress Programmable Logic Products
Note:
1.
Upper limit of typical gates is calculated by assuming only 10% of the channel memory is used.
2.
Standby ICC values are with PLL not utilized, no output load and stable inputs
Delta39K ISR CPLD Family Members
Device
Typical
Gates[1]
Macrocells
Cluster
memory
(Kbits)
Channel
memory
(Kbits)
Maximum
I/O Pins
fMAX2
(MHz)
Speed - tPD
Pin-to-Pin
(ns)
Standby ICC
[2]
TA=25°C
3.3/2.5V
1.8V
39K15
8K–24K
256
32
8
134
256
6.5
10 mA
100
A
39K30
16K–48K
512
64
16
176
238
7.0
10 mA
200
A
39K50
23K–72K
768
96
24
218
238
7.0
10 mA
300
A
39K100
46K–144K
1536
192
48
302
222
7.5
10 mA
600
A
39K165
77K–241K
2560
320
80
386
181
8.5
10 mA
1250
A
39K200
92K–288K
3072
384
96
428
181
8.5
10 mA
1250
A
39K250
115K–361K
3840
480
120
470
167
8.5
10 mA
1500
A
39K350
161K–505K
5376
672
168
520
154
9.0
10 mA
2100
A
相关PDF资料
PDF描述
CY39050V256-222BBC LOADABLE PLD, 7 ns, PBGA256
CY39050V388-222MGC LOADABLE PLD, 7 ns, PBGA388
CY39050V484-222MBC LOADABLE PLD, 7 ns, PBGA484
CY39050Z208-222NC LOADABLE PLD, 7 ns, PQFP208
CY39050Z256-222BBC LOADABLE PLD, 7 ns, PBGA256
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