参数资料
型号: CY39050V208-222NTC
厂商: CYPRESS SEMICONDUCTOR CORP
元件分类: PLD
英文描述: LOADABLE PLD, 7 ns, PQFP208
封装: THERMALLY ENHANCED, QFP-208
文件页数: 9/57页
文件大小: 1166K
代理商: CY39050V208-222NTC
PRELIMINARY
Delta39K ISR
CPLD Family
Document #: 38-03039 Rev. **
Page 17 of 57
Notes:
8.
PCI spec (rev 2.2) requires the IDSEL pin to have capacitance less than or equal to 8 pF. Document titled “Delta39K Pin Tables” identifies all the I/O pins, in a
given package, which can be used as IDSEL in a PCI design. All other I/O pins meet the PCI requirement of capacitance less than or equal to 10 pf.
9.
The number of I/Os which can be used in each I/O bank depends on the type of I/O standards and the number of VCCIO and GND pins being used. Please refer
to the application note titled “Delta39K Family Device I/O Standards and Configurations” for details.
The source current limit per I/O bank per Vccio pin is 165 mA
The sink current limit per I/O bank per GND pin is 230 mA
10. See “Power-up Sequence Requirements” below for VCCIO requirement.
11. 25
resistor terminated to termination voltage of 1.5V.
Capacitance
Parameter
Description
Test Conditions
Min.
Max.
Unit
CI/O
Input/Output Capacitance
Vin=VCCIO @ f=1 MHz 25°C
10
pF
CCLK
Clock Signal Capacitance
Vin=VCCIO @ f=1 MHz 25°C
5
12
pF
CPCI
PCI Compliant[8] Capacitance
Vin=VCCIO @ f=1 MHz 25°C
8
pF
DC Characteristics (IO)[9]
Input/
Output
Standard
VREF (V)
VCCIO
(V)
VOH (V)
VOL (V)
VIH (V)
VIL (V)
Mi
n
.
Max
.
@ IOH =VOH (min.)
@ IOL =
VOL
(max.)
Min.
Max.
Min.
Max.
LVTTL
N/A
3.3
–4 mA
2.4
4 mA
0.4
2.0 V
VCCIO+0.3 –0.3V
0.8V
LVCMOS
3.3
–0.1 mA
VCCIO–0.2v
0.1 mA
0.2
2.0 V
VCCIO+0.3 –0.3V
0.8V
LVCMOS3
3.0
–0.1 mA
VCCIO–0.2v
0.1mA
0.2
2.0 V
VCCIO+0.3 –0.3V
0.8V
LVCMOS2
2.5
–0.1 mA
2.1
0.1 mA
0.2
1.7 V
VCCIO+0.3 –0.3V
0.7V
–1.0 mA
2.0
1.0 mA
0.4
–2.0 mA
1.7
2.0 mA
0.7
LVCMOS18
1.8
–0.1 mA
VCCIO–0.2v
0.1mA
0.2
0.65VCCIO VCCIO+0.3 –0.3V
0.35VCCIO
– 2 mA
VCCIO–0.45v 2.0 mA
0.45
3.3V PCI
3.3
–0.5 mA
0.9VCCIO
1.5 mA
0.1VCCIO 0.5VCCIO VCCIO+0.5 –0.5V
0.3VCCIO
GTL+
0.9
1.1
Note 10
Note 11
0.6
VREF+0.2
VREF–0.2
SSTL3 I
1.3
1.7
3.3
–8 mA
VCCIO–1.1v
8 mA
0.7
VREF+0.2 VCCIO+0.3 –0.3V
VREF–0.2
SSTL3 II
1.3
1.7
3.3
–16 mA
VCCIO–0.9v
16 mA
0.5
VREF+0.2 VCCIO+0.3 –0.3V
VREF–0.2
SSTL2 I
1.15 1.35
2.5
–7.6 mA
VCCIO–0.62v 7.6 mA
0.54
VREF+1.8 VCCIO+0.3 –0.3V VREF–0.18
SSTL2 II
1.15 1.35
2.5
–15.2 mA VCCIO–0.43v 15.2 mA
0.35
VREF+1.8 VCCIO+0.3 –0.3V VREF–0.18
HSTL I
0.68
0.9
1.5
–8 mA
VCCIO–0.4v
8 mA
0.4
VREF+1.0 VCCIO+0.3 –0.3V
VREF–0.1
HSTL II
0.68
0.9
1.5
–16 mA
VCCIO–0.4v
16 mA
0.4
VREF+1.0 VCCIO+0.3 –0.3V
VREF–0.1
HSTL III
0.68
0.9
1.5
–8 mA
VCCIO–0.4v
24 mA
0.4
VREF+1.0 VCCIO+0.3 –0.3V
VREF–0.1
HSTL IV
0.68
0.9
1.5
–8 mA
VCCIO–0.4v
48 mA
0.4
VREF+1.0 VCCIO+0.3 –0.3V
VREF–0.1
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