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参数资料
| 型号： | CY7C1177V18-333BZXC |
| 厂商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分类： | SRAM |
| 英文描述： | 18-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency) |
| 中文描述： | 2M X 9 DDR SRAM, 0.45 ns, PBGA165 |
| 封装： | 13 X 15 MM, 1.40 MM HEIGHT, LEAD FREE, MO-216, FBGA-165 |
| 文件页数： | 11/27页 |
| 文件大小： | 648K |
| 代理商： | CY7C1177V18-333BZXC |
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CY7C1166V18, CY7C1177V18
CY7C1168V18, CY7C1170V18
Document Number: 001-06620 Rev. *D
Page 19 of 27
Power Up Sequence in DDR-II+ SRAM
DDR-II+ SRAMs must be powered up and initialized in a
predefined manner to prevent undefined operations. During
power up, when the DOFF is tied HIGH, the DLL gets locked after
2048 cycles of stable clock.
Power Up Sequence
■ Apply power with DOFF tied HIGH (all other inputs can be HIGH
or LOW)
Apply VDD before VDDQ
Apply VDDQ before VREF or at the same time as VREF
■ Provide stable power and clock (K, K) for 2048 cycles to lock
the DLL.
DLL Constraints
■ DLL uses K clock as its synchronizing input. The input must
have low phase jitter, which is specified as tKC Var.
■ The DLL functions at frequencies down to 120 MHz.
■ If the input clock is unstable and the DLL is enabled, then the
DLL may lock onto an incorrect frequency, causing unstable
SRAM behavior. To avoid this, provide 2048 cycles stable clock
to relock to the desired clock frequency.
Power Up Waveforms
Figure 5. Power Up Waveforms
K
Fix HIGH (tie to VDDQ)
VDD/VDDQ
DOFF
Clock Start (Clock Starts after VDD/VDDQ is Stable)
Unstable Clock
> 2048 Stable Clock
Start Normal
Operation
~ ~
VDD/VDDQ Stable (< + 0.1V DC per 50 ns)
相关PDF资料 |
PDF描述 |
|---|---|
| CY7C1177V18-333BZXI | 18-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency) |
| CY7C1170V18 | 18-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency) |
| CY7C1177V18 | 18-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency) |
| CY7C1215H-100AXC | 1-Mbit (32K x 32) Pipelined Sync SRAM |
| CY7C1215H-100AXI | 1-Mbit (32K x 32) Pipelined Sync SRAM |
相关代理商/技术参数 |
参数描述 |
|---|---|
| CY7C1214F-100AC | 制造商:Cypress Semiconductor 功能描述: |
| CY7C1214F-100ACT | 制造商:Cypress Semiconductor 功能描述: |
| CY7C1215F-166AC | 制造商:Rochester Electronics LLC 功能描述:1MB (32K X 32) 3.3V PIPELINE SCD - Bulk 制造商:Cypress Semiconductor 功能描述: |
| CY7C1215H-166AXC | 制造商:Cypress Semiconductor 功能描述:SRAM SYNC SGL 3.3V 1MBIT 32KX32 3.5NS 100TQFP - Bulk |
| CY7C1217H-133AXC | 制造商:Cypress Semiconductor 功能描述:SRAM SYNC QUAD 3.3V 1.125MBIT 32KX36 7.5NS 100TQFP - Bulk |
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