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参数资料
| 型号： | CY7C1177V18-333BZXC |
| 厂商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分类： | SRAM |
| 英文描述： | 18-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency) |
| 中文描述： | 2M X 9 DDR SRAM, 0.45 ns, PBGA165 |
| 封装： | 13 X 15 MM, 1.40 MM HEIGHT, LEAD FREE, MO-216, FBGA-165 |
| 文件页数： | 2/27页 |
| 文件大小： | 648K |
| 代理商： | CY7C1177V18-333BZXC |
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CY7C1166V18, CY7C1177V18
CY7C1168V18, CY7C1170V18
Document Number: 001-06620 Rev. *D
Page 10 of 27
Write Cycle Descriptions
BWS0/
NWS0
BWS1/
NWS1
K
Comments
L
L–H
–
During the Data portion of a write sequence
:
CY7C1166V18
both nibbles (D
[7:0]) are written into the device.
CY7C1168V18
both bytes (D
[17:0]) are written into the device.
L
–
L-H During the Data portion of a write sequence
:
CY7C1166V18
both nibbles (D
[7:0]) are written into the device.
CY7C1168V18
both bytes (D
[17:0]) are written into the device.
L
H
L–H
–
During the Data portion of a write sequence
:
CY7C1166V18
only the lower nibble (D
[3:0]) is written into the device, D[7:4] remains unaltered.
CY7C1168V18
only the lower byte (D
[8:0]) is written into the device, D[17:9] remains unaltered.
L
H
–
L–H During the Data portion of a write sequence
:
CY7C1166V18
only the lower nibble (D
[3:0]) is written into the device, D[7:4] remains unaltered.
CY7C1168V18
only the lower byte (D
[8:0]) is written into the device, D[17:9] remains unaltered.
H
L
L–H
–
During the Data portion of a write sequence
:
CY7C1166V18
only the upper nibble (D
[7:4]) is written into the device, D[3:0] remains unaltered.
CY7C1168V18
only the upper byte (D
[17:9]) is written into the device, D[8:0] remains unaltered.
H
L
–
L–H During the Data portion of a write sequence
:
CY7C1166V18
only the upper nibble (D
[7:4]) is written into the device, D[3:0] remains unaltered.
CY7C1168V18
only the upper byte (D
[17:9]) is written into the device, D[8:0] remains unaltered.
H
L–H
–
No data is written into the devices during this portion of a write operation.
H
–
L–H No data is written into the devices during this portion of a write operation.
BWS0
K
Comments
L
L-H
–
During the Data portion of a Write sequence
, the single byte (D
[8:0]) is written into the device.
L
–
L-H
During the Data portion of a Write sequence
, the single byte (D
[8:0]) is written into the device.
H
L-H
–
No data is written into the device during this portion of a Write operation.
H
–
L-H
No data is written into the device during this portion of a Write operation.
Note
8. Is based on a write cycle was initiated in accordance with the Write Cycle Description Truth Table. Alter NWS0, NWS1, BWS0, BWS1, BWS2, and BWS3 on different
portions of a write cycle, as long as the setup and hold requirements are achieved.
相关PDF资料 |
PDF描述 |
|---|---|
| CY7C1177V18-333BZXI | 18-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency) |
| CY7C1170V18 | 18-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency) |
| CY7C1177V18 | 18-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency) |
| CY7C1215H-100AXC | 1-Mbit (32K x 32) Pipelined Sync SRAM |
| CY7C1215H-100AXI | 1-Mbit (32K x 32) Pipelined Sync SRAM |
相关代理商/技术参数 |
参数描述 |
|---|---|
| CY7C1214F-100AC | 制造商:Cypress Semiconductor 功能描述: |
| CY7C1214F-100ACT | 制造商:Cypress Semiconductor 功能描述: |
| CY7C1215F-166AC | 制造商:Rochester Electronics LLC 功能描述:1MB (32K X 32) 3.3V PIPELINE SCD - Bulk 制造商:Cypress Semiconductor 功能描述: |
| CY7C1215H-166AXC | 制造商:Cypress Semiconductor 功能描述:SRAM SYNC SGL 3.3V 1MBIT 32KX32 3.5NS 100TQFP - Bulk |
| CY7C1217H-133AXC | 制造商:Cypress Semiconductor 功能描述:SRAM SYNC QUAD 3.3V 1.125MBIT 32KX36 7.5NS 100TQFP - Bulk |
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