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参数资料
| 型号： | DC859A |
| 厂商： | Linear Technology |
| 文件页数： | 23/32页 |
| 文件大小： | 0K |
| 描述： | EVAL BOARD FOR LTC4267 |
| 设计资源： | DC859A Design File DC859A Schematic |
| 标准包装： | 1 |
| 主要目的： | 电源管理，以太网供电（POE） |
| 嵌入式： | 否 |
| 已用 IC / 零件： | LTC4267 |
| 已供物品： | 板 |
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LTC4267
3
4267fc
The ● denotes the specications which apply over the full operating
temperature range, otherwise specications are at TA = 25°C. (Note 3)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
VMARGIN
VCLAMP1mA – VTURNON Margin
●
0.05
0.6
V
IVPORTN_ON
VPORTN Supply Current when ON
VPORTN = –48V, POUT, PWRGD, SIGDISA Floating
●
3
mA
IPVCC_ON
PVCC Supply Current
(Note 7)
Normal Operation
VITH/RUN – PGND = 1.3V
●
240
350
A
Start-Up
PVCC – PGND = VTURNON – 100mV
●
40
90
A
IVPORTN_CLASS VPORTN Supply Current
VPORTN = –17.5V, POUT Tied to VPORTP, RCLASS,
●
0.35
0.5
0.65
mA
During Classication
SIGDISA Floating (Note 8)
ICLASS
Current Accuracy
10mA < ICLASS < 40mA, –12.5V ≤ VPORTN ≤ –21V
●
±3.5
%
During Classication
(Notes 9, 10)
RSIGNATURE
Signature Resistance
–1.5V ≤ VPORTN ≤ – 9.5V, POUT Tied to VPORTP,
●
23.25
26.00
kΩ
IEEE 802.3af 2-Point Measurement (Notes 4, 5)
RINVALID
Invalid Signature Resistance
–1.5V ≤ VPORTN ≤ – 9.5V, SIGDISA and POUT Tied to
●
9
11.8
kΩ
VPORTP, IEEE 802.3af 2-Point Measurement
(Notes 4, 5)
VIH
Signature Disable
With Respect to VPORTN
●
3
57
V
High Level Input Voltage
High Level Invalidates Signature (Note 11)
VIL
Signature Disable
With Respect to VPORTN
●
0.45
V
Low Level Input Voltage
Low Level Enables Signature
RINPUT
Signature Disable, Input Resistance
With Respect to VPORTN
●
100
kΩ
VPG_OUT
Power Good Output Low Voltage
I = 1mA VPORTN = –48V,
●
0.5
V
PWRGD Referenced to VPORTN
Power Good Trip Point
VPORTN = –48V, Voltage between VPORTN and POUT (Note 10)
VPG _FALL
POUT Falling
●
1.3
1.5
1.7
V
VPG_RISE
POUT Rising
●
2.7
3.0
3.3
V
IPG_LEAK
Power Good Leakage Current
VPORTN = 0V, PWRGD FET Off, VPWRGD = 57V
●
1
A
RON
On-Resistance
I = 300mA, VPORTN = –48V, Measured from
1.0
1.6
Ω
VPORTN to POUT (Note 10)
●
2
Ω
VITHSHDN
Shutdown Threshold (at ITH/RUN)
PVCC – PGND = VTURNON + 100mV
●
0.15
0.28
0.45
V
ITHSTART
Start-Up Current Source at ITH/RUN
VITH/RUN – PGND = 0V, PVCC – PGND = 8V
0.2
0.3
0.4
A
VFB
Regulated Feedback Voltage
Referenced to PGND, PVCC – PGND = 8V (Note 12)
●
0.780
0.800
0.812
V
IFB
VFB Input Current
PVCC – PGND = 8V (Note 12)
10
50
nA
gm
Error Amplier Transconductance
ITH/RUN Pin Load = ±5A (Note 12)
200
333
500
A/V
VO(LINE)
Output Voltage Line Regulation
VTURNOFF < PVCC < VCLAMP (Note 12)
0.05
mV/V
VO(LOAD)
Output Voltage Load Regulation
ITH/RUN Sinking 5A, PVCC – PGND = 8V (Note 12)
3
mV/A
ITH/RUN Sourcing 5A, PVCC – PGND = 8V (Note 12)
3
mV/A
IPOUT_LEAK
POUT Leakage
VPORTN = 0V, Power MOSFET Off,
●
150
A
POUT = 57V (Note 13)
ILIM_HI
Input Current Limit, High Level
VPORTN = –48V, POUT = –43V (Note 14, 15)
0°C ≤ TA ≤ 70°C
●
325
375
400
mA
– 40°C ≤ TA ≤ 85°C
●
300
375
400
mA
ILIM_LO
Input Current Limit, Low Level
VPORTN = –48V, POUT = –43V (Note 14, 15)
●
80
140
180
mA
fOSC
Oscillator Frequency
VITH/RUN – PGND = 1.3V, PVCC – PGND = 8V
180
200
240
kHz
DCON(MIN)
Minimum Switch On Duty Cycle
VITH/RUN – PGND = 1.3V, VFB – PGND = 0.8V,
6
8
%
PVCC – PGND = 8V
DCON(MAX)
Maximum Switch On Duty Cycle
VITH/RUN – PGND = 1.3V, VFB – PGND = 0.8V,
70
80
90
%
PVCC – PGND = 8V
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