参数资料
型号: DS1873T+
厂商: Maxim Integrated
文件页数: 19/86页
文件大小: 0K
描述: IC CTLR SFP+ ANLG LDD 28-TQFN
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 60
类型: 激光二极管控制器
通道数: 1
电源电压: 2.85 V ~ 3.9 V
电流 - 电源: 2.5mA
工作温度: -40°C ~ 95°C
封装/外壳: 28-WFQFN 裸露焊盘
供应商设备封装: 28-TQFN-EP(5x5)
包装: 托盘
安装类型: 表面贴装
其它名称: 90-1873T+000
SFP+ Controller with Analog LDD Interface
Low-Voltage Operation
The DS1873 contains two power-on reset (POR) levels.
The lower level is a digital POR (POD) and the higher
level is an analog POR (POA). At startup, before the
supply voltage rises above POA, the outputs are dis-
abled, all SRAM locations are set to their defaults,
shadowed EEPROM (SEE) locations are zero, and all
analog circuitry is disabled. When V CC reaches POA,
the SEE is recalled, and the analog circuitry is enabled.
While V CC remains above POA, the device is in its nor-
mal operating state, and it responds based on its non-
volatile configuration. If during operation V CC falls
below POA, but is still above POD, then the SRAM
retains the SEE settings from the first SEE recall, but the
device analog is shut down and the outputs disabled. If
the supply voltage recovers back above POA, then the
device immediately resumes normal operation. If the
supply voltage falls below POD, then the device SRAM
is placed in its default state and another SEE recall is
required to reload the nonvolatile settings. The EEP-
ROM recall occurs the next time V CC exceeds POA.
Figure 9 shows the sequence of events as the voltage
varies.
Any time V CC is above POD, the I 2 C interface can be
used to determine if V CC is below the POA level. This is
accomplished by checking the RDYB bit in the STATUS
(Lower Memory, Register 6Eh) byte. RDYB is set when
V CC is below POA; when V CC rises above POA, RDYB
is timed (within 500μs) to go to 0, at which point the
part is fully functional.
For all device addresses sourced from EEPROM (Table
02h, Register 8Ch), the default device address is A2h
until V CC exceeds POA, allowing the device address to
be recalled from the EEPROM.
Power-On Analog (POA)
POA holds the DS1873 in reset until V CC is at a suitable
level (V CC > POA) for the device to accurately measure
with its ADC and compare analog signals with its quick-
trip monitors. Because V CC cannot be measured by the
ADC when V CC is less than POA, POA also asserts the
VCC LO alarm, which is cleared by a V CC ADC conver-
sion greater than the customer-programmable V CC
alarm LO ADC limit. This allows a programmable limit to
ensure that the headroom requirements of the trans-
ceiver are satisfied during a slow power-up. The TXF
output does not latch until there is a conversion above
V CC low limit. The POA alarm is nonmaskable. The TXF
output is asserted when V CC is below POA. See the
Low-Voltage Operation section for more information.
Delta-Sigma Outputs
Four delta-sigma outputs are provided: MOD DAC,
BIAS DAC, DAC1, and DAC2. With the addition of an
external RC filter, these outputs provide 10-bit resolu-
tion analog outputs with the full-scale range set by the
input REFIN. Each output is either manually controlled
or controlled using a temperature-indexed LUT, or in
the case of the BIAS DAC, controlled by the APC loop.
A delta-sigma is a digital output using pulse-density
modulation. It provides much lower output ripple than a
V POA
V CC
V POD
SEE RECALL
SEE RECALL
SEE
PRECHARGED
TO 0
RECALLED VALUE
PRECHARGED TO 0
RECALLED VALUE
PRECHARGED
TO 0
Figure 9. Low-Voltage Hysteresis Example
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