参数资料
型号: DS1873T+
厂商: Maxim Integrated
文件页数: 21/86页
文件大小: 0K
描述: IC CTLR SFP+ ANLG LDD 28-TQFN
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 60
类型: 激光二极管控制器
通道数: 1
电源电压: 2.85 V ~ 3.9 V
电流 - 电源: 2.5mA
工作温度: -40°C ~ 95°C
封装/外壳: 28-WFQFN 裸露焊盘
供应商设备封装: 28-TQFN-EP(5x5)
包装: 托盘
安装类型: 表面贴装
其它名称: 90-1873T+000
SFP+ Controller with Analog LDD Interface
MOD, DAC1, AND DAC2 OFFSET LUTs (04h, 07h, AND 08h)
EIGHT REGISTERS PER DAC
MOD, DAC1, AND DAC2 OFFSET LUTs (04h, 07h, AND 08h)
EIGHT REGISTERS PER DAC
1023
EACH OFFSET REGISTER CAN BE INDEPENDENTLY
SET BETWEEN 0 AND 1020. 1020 = 4 x FFh. THIS
EXAMPLE ILLUSTRATES POSITIVE TEMPCO.
FEh
FFh
DAC
LUT
1023
EACH OFFSET REGISTER CAN BE INDEPENDENTLY SET BETWEEN
0 AND 1020. 1020 = 4 x FFh. THIS EXAMPLE ILLUSTRATES POSITIVE
AND NEGATVE TEMPCO.
767
511
255
F8h
DAC
LUT
BITS
7:0
F9h
DAC
LUT
BITS
7:0
FAh
DAC
LUT
BITS
7:0
FBh
DAC
LUT
BITS
7:0
FCh
DAC
LUT
BITS
7:0
FDh
DAC
LUT
BITS
7:0
DAC
LUT
BITS
7:0
BITS
7:0
767
511
255
F8h
DAC
LUT
BITS
7:0
F9h
DAC
LUT
BITS
7:0
FAh
DAC
LUT
BITS
7:0
FBh
DAC
LUT
BITS
7:0
FCh
DAC
LUT
BITS
7:0
FDh
DAC
LUT
BITS
7:0
FEh
DAC
LUT
BITS
7:0
FFh
DAC
LUT
BITS
7:0
0
-40 ° C
-8 ° C
+8 ° C
+24 ° C +40 ° C +56 ° C +70 ° C +88 ° C +104 ° C
0
-40 ° C
-8 ° C
+8 ° C
+24 ° C +40 ° C +56 ° C +70 ° C +88 ° C +104 ° C
Figure 12. MOD, DAC1, and DAC2 Offset LUTs
Digital I/O Pins
Five digital input and five digital output pins are provid-
ed for monitoring and control.
LOS, LOSOUT
By default (LOSC = 1, Table 02h, Register 89h), the
LOS pin is used to convert a standard comparator out-
put for loss of signal (LOS) to an open-collector output.
This means the mux shown in the Block Diagram by
default selects the LOS pin as the source for the
LOSOUT output transistor. The output of the mux can
be read in the STATUS byte (Lower Memory,
Register 6Eh) as the RXL bit. The RXL signal can be
inverted (INV LOS = 1) before driving the open-drain
output transistor using the XOR gate provided. Setting
LOSC = 0 configures the mux to be controlled by LOS
LO, which is driven by the output of the LOS quick trip
(Table 02h, Registers BEh and BFh). The mux setting
(stored in EEPROM) does not take effect until V CC >
POA, allowing the EEPROM to recall.
IN1, RSEL, OUT1, RSELOUT
The digital input IN1 and RSEL pins primarily serve to
meet the rate-select requirements of SFP and SFP+.
They also serve as general-purpose inputs. OUT1 and
RSELOUT are driven by a combination of the IN1,
RSEL, and logic dictated by control registers in the
EEPROM (Figure 14). The levels of IN1 and RSEL can
be read using the STATUS register (Lower Memory,
Register 6Eh). The open-drain output OUT1 can be
controlled and/or inverted using the CNFGB register
(Table 02h, Register 8Ah). The open-drain RSELOUT
output is software-controlled and/or inverted through
the STATUS register and CNFGA register (Table 02h,
Register 89h). External pullup resistors must be provid-
ed on OUT1 and RSELOUT to realize high logic levels.
______________________________________________________________________________________
21
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