参数资料
型号: DS1873T+
厂商: Maxim Integrated
文件页数: 27/86页
文件大小: 0K
描述: IC CTLR SFP+ ANLG LDD 28-TQFN
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 60
类型: 激光二极管控制器
通道数: 1
电源电压: 2.85 V ~ 3.9 V
电流 - 电源: 2.5mA
工作温度: -40°C ~ 95°C
封装/外壳: 28-WFQFN 裸露焊盘
供应商设备封装: 28-TQFN-EP(5x5)
包装: 托盘
安装类型: 表面贴装
其它名称: 90-1873T+000
SFP+ Controller with Analog LDD Interface
Table 08h contains a temperature-indexed LUT for
control of DAC2. The LUT has 36 entries that determine
the DAC setting in 4°C windows between -40°C and
+100°C.
Auxiliary Memory (device A0h) contains 256 bytes of
EE memory accessible from address 00h –FFh. It is
selected with the device address of A0h.
See the Register Descriptions section for more com-
plete details of each byte ’s function, as well as for
read/write permissions for each byte.
Shadowed EEPROM
Many NV memory locations (listed within the Register
Descriptions section) are actually shadowed EEPROM
that are controlled by the SEEB bit in Table 02h,
Register 80h.
The DS1873 incorporates shadowed-EEPROM memory
locations for key memory addresses that can be written
many times. By default the shadowed-EEPROM bit,
SEEB, is not set and these locations act as ordinary EEP-
ROM. By setting SEEB, these locations function like
SRAM cells, which allow an infinite number of write cycles
without concern of wearing out the EEPROM. Setting
SEEB also eliminates the requirement for the EEPROM
write time, t WR . Because changes made with SEEB
enabled do not affect the EEPROM, these changes are
not retained through power cycles. The power-on value is
the last value written with SEEB disabled. This function
can be used to limit the number of EEPROM writes during
calibration or to change the monitor thresholds periodical-
ly during normal operation helping to reduce the number
of times EEPROM is written. Figure 18 indicates which
locations are shadowed EEPROM.
I 2 C ADDRESS A0h
00h
I 2 C ADDRESS A2h (DEFAULT)
00h
LOWER
MEMORY
PASSWORD ENTRY
(PWE) (4 BYTES)
TABLE-SELECT
NOTE 1: IF ASEL = 0, THEN THE MAIN DEVICE I 2 C SLAVE ADDRESS IS A2h.
IF ASEL = 1, THEN THE MAIN DEVICE I 2 C SLAVE ADDRESS IS DETERMINED BY THE VALUE IN
TABLE 02h, REGISTER 8Ch.
NOTE 2: TABLE 00h DOES NOT EXIST.
NOTE 3: ALARM-ENABLE ROW CAN BE CONFIGURED TO EXIST AT TABLE 01h OR TABLE 05h USING THE
MASK BIT IN TABLE 02h, REGISTER 89h.
EEPROM
(256 BYTES)
BYTE
7Fh
80h
80h
80h
80h TABLE 06h
80h
80h
TRACKING ERROR
TABLE 08h
TABLE 04h
LOOKUP TABLE
DAC2 LUT
TABLE 01h
EEPROM
(120 BYTES)
TABLE 02h
NONLOOKUP
TABLE CONTROL
MOD
LOOKUP TABLE
(72 BYTES)
(36 BYTES) A3h
TABLE 07h
DAC1 LUT
A3h
AND
F7h
CONFIGURATION
REGISTERS
C7h
C7h
FFh
F8h
ALARM-
ENABLE ROW
(8 BYTES) FFh
FFh
F8h
MOD OFFSET
LUT
FFh
F8h TABLE 05h
ALARM-ENABLE ROW
(8 BYTES) FFh
F8h
HBIAS LUT
FFh
F8h
DAC1 OFFSET
LUT
FFh
F8h
DAC2 OFFSET
LUT
FFh
Figure 18. Memory Map
______________________________________________________________________________________
27
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