参数资料
型号: DS1873T+
厂商: Maxim Integrated
文件页数: 57/86页
文件大小: 0K
描述: IC CTLR SFP+ ANLG LDD 28-TQFN
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 60
类型: 激光二极管控制器
通道数: 1
电源电压: 2.85 V ~ 3.9 V
电流 - 电源: 2.5mA
工作温度: -40°C ~ 95°C
封装/外壳: 28-WFQFN 裸露焊盘
供应商设备封装: 28-TQFN-EP(5x5)
包装: 托盘
安装类型: 表面贴装
其它名称: 90-1873T+000
SFP+ Controller with Analog LDD Interface
Table 02h, Register 86h–87h: DAC2 VALUE
FACTORY DEFAULT
READ ACCESS
WRITE ACCESS
MEMORY TYPE
0000h
PW2 or (PW1 and RWTBL246) or (PW1 and RTBL246)
(PW2 and DAC2 EN = 0) or (PW1 and RWTBL246 and DAC2 EN = 0)
Volatile
86h
87h
0
2 7
0
2 6
0
2 5
0
2 4
0
2 3
0
2 2
0
2 1
2 8
2 0
BIT 7
BIT 0
The digital value used for DAC2. It is the result of LUT8 plus DAC2 OFFSET times 4 recalled from Table 08h at the
adjusted memory address found in TINDEX. This register is updated at the end of the temperature conversion.
DAC2 VALUE = LUT8 + DAC2 OFFSET 4
Table 02h, Register 88h: UPDATE RATE
V DAC2 =
V REFIN
1024
DAC2 VALUE
FACTORY DEFAULT
READ ACCESS
WRITE ACCESS
MEMORY TYPE
00h
PW2 or (PW1 and RWTBL2) or (PW1 and RTBL2)
PW2 or (PW1 and RWTBL2)
Nonvolatile (SEE)
88h
SEE
SEE
SEE
SEE
APC_SR 3
APC_SR 2
APC_SR 1
APC_SR 0
BIT 7
BITS 7:4
BITS 3:0
BIT 0
SEE
APC_SR[3:0]: 4-bit sample rate for comparison of APC control. Defines the sample rate for comparison of
APC control.
The quick-trip comparator uses a 1.6μs window to sample each input. After an APC comparison that requires an
update to the BIAS DAC, a settling time (as calculated below) is required to allow for the feedback on BMD (MON2)
to stabilize. This time is dependent on the time constant of the filter pole used for the delta-to-sigma BIAS output.
During the timing of the settling rate, comparisons of APC comparisons of BMD are ignored until 32 sample periods
(t REP ) have passed.
SettlingTime = 51.2μs x (APC_SR[3:0] + 1)
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