参数资料
型号: DS1873T+
厂商: Maxim Integrated
文件页数: 20/86页
文件大小: 0K
描述: IC CTLR SFP+ ANLG LDD 28-TQFN
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 60
类型: 激光二极管控制器
通道数: 1
电源电压: 2.85 V ~ 3.9 V
电流 - 电源: 2.5mA
工作温度: -40°C ~ 95°C
封装/外壳: 28-WFQFN 裸露焊盘
供应商设备封装: 28-TQFN-EP(5x5)
包装: 托盘
安装类型: 表面贴装
其它名称: 90-1873T+000
SFP+ Controller with Analog LDD Interface
MOD and DAC1 high-resolution LUTs each have 2°C
DAC
3.24k Ω
3.24k Ω
0.01 μ F
OUTPUT
0.01 μ F
resolution. The DAC2 high-resolution LUT has 4°C reso-
lution. The OFFSET LUTs are located in the upper eight
registers (F8h–FFh) of the table containing each high-
resolution LUT. MOD DAC, DAC1 VALUE, and DAC2
DS1873
Figure 10. Recommended RC Filter for DAC1/DAC2
standard digital PWM output given the same clock rate
and filter components. Before t INIT , the DAC outputs
are high impedance.
The external RC filter components are chosen based
on ripple requirements, output load, delta-sigma fre-
quency, and desired response time. A recommended
filter is shown in Figure 10.
The DS1873’s delta-sigma outputs are 10 bits. For illus-
trative purposes, a 3-bit example is provided. Each
possible output of this 3-bit delta-sigma DAC is given in
Figure 11.
In LUT mode, MOD, DAC1, and DAC2 are each con-
trolled by an LUT with high-temperature resolution and
an OFFSET LUT with lower temperature resolution. The
0
1
2
3
4
5
6
7
Figure 11. 3-Bit Delta-Sigma Example
VALUE are determined as follows:
MOD DAC = MOD LUT + 4 x (MOD OFFSET LUT)
DAC1 VALUE = DAC1 LUT + 4 x (DAC1 OFFSET LUT)
DAC2 VALUE = DAC1 LUT + 4 x (DAC1 OFFSET LUT)
Example calculation for MOD DAC:
Assumptions:
1) Temperature is 43°C.
2) Table 04h (MOD OFFSET LUT), Register FCh = 2Ah.
3) Table 04h (MOD LUT), Register A9h = 7Bh.
Because the temperature is 43°C, the MOD LUT index
is A9h and the MOD OFFSET LUT index is FCh.
MOD DAC = 7Bh + 4 x 2Ah = 123h = 291
When temperature controlled, the DACs are updated
after each temperature conversion.
The reference input, REFIN, is the supply voltage for all
four DACs. The voltage connected to REFIN and its
decoupling must be able to support the edge rate
requirements of the delta-sigma outputs.
20
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