参数资料
型号: DS26900LN+
厂商: Maxim Integrated Products
文件页数: 11/49页
文件大小: 0K
描述: IC JTAG MUX/SWITCH 144-LQFP
标准包装: 90
系列: *
功能: *
电压电源: 单电源
电压 - 电源,单路/双路(±): 3.14 V ~ 3.47 V
电流 - 电源: *
工作温度: *
安装类型: 表面贴装
封装/外壳: 144-LQFP
供应商设备封装: 144-LQFP(20x20)
包装: 托盘
__________________________________________________________________________________________DS26900
19
3. Functional Description
The DS26900 is a star (radial) configuration system-level JTAG signal multiplexer, which provides connectivity
between a master port and secondary ports. The master port, which has been granted control of the switch, can
also treat the unselected master ports as secondary ports.
There are three possible master ports: ETM (External Test Master), TM1 (Test Master 1), and TM2 (Test Master 2).
ETM functions as the primary master with TM1 and TM2 available as alternative masters. Direct arbitration
determines which of the three possible masters can control the switch. ETM has the highest priority whenever there
is a conflict over which master port can control the device. See Section 4.2 for more information on master port
arbitration.
JTAG connectivity is provided for up to 18 secondary ports per package as well as two additional secondary ports,
TM1 and TM2, when they are not functioning as a master. Two DS26900s can be cascaded to provide additional
secondary ports. The DS26900 can be in one of four modes: Single-Package Mode, Cascade-Master Mode,
Cascade-Extension Mode, and Deselect Mode.
The DS26900 contains two TAP controllers: one as part of the primary switch function and one to control the
traditional JTAG interface at the periphery of the device for manufacturing test purposes.
Configuration of the DS26900 is accomplished via the Switch TAP Controller. Configuration options include
sensing the presence of secondary ports, addressing the target secondary port, reading/writing scratchpad
registers, GPIO pin read/write, generating port resets, configuring path and signaling inversion options, and placing
the DS26900 in transparent mode for direct communications with the secondary port.
Communications with the DS26900 is accomplished via a master port while asserting the associated ports
configure signal (
TRST1, TRST2, or ECFG) low. Connected ports (cards) are detected by sensing the port’s TMS
pullup resistor, and the results are available in the Port Detection Register (PDR). Selection of the desired port is
accomplished by setting the address in the Secondary Port Selection Register (SPSR). Once the destination port
selection bits are written, the Switch TAP Controller is returned to idle/reset state and the configuration signal
(
TRST) is asserted high. The DS26900 routes the JTAG signal set (clock, data-in, data-out, mode select, and reset)
from the arbitrated master to the selected destination port with controlled timing relationships. A reset for the
secondary port can be generated by writing a register bit after a port address is selected. Test masters can be
swapped without affecting the logic state of the selected secondary port.
The DS26900 also contains traditional boundary scan circuitry at the periphery of the package for board
manufacturing tests. See Section 9. This periphery boundary scan circuitry is independent and has priority over the
operation of the master/slave multiplexer. It contains a separate TAP controller with a 3-bit wide instruction code
register. Signals associated with the periphery boundary scan circuitry are
PTRST, PTMS, PTCK, PTDI, and PTDO.
The DS26900 switch is designed to work at clock rates up to 50MHz. The arbitrated master is the source of the
operating clock. However, the separate periphery JTAG function, as described above, operates at a maximum
frequency of 10MHz.
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