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参数资料
| 型号： | DS26900LN+ |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 18/49页 |
| 文件大小： | 0K |
| 描述： | IC JTAG MUX/SWITCH 144-LQFP |
| 标准包装： | 90 |
| 系列： | * |
| 功能： | * |
| 电压电源： | 单电源 |
| 电压 - 电源，单路/双路(±)： | 3.14 V ~ 3.47 V |
| 电流 - 电源： | * |
| 工作温度： | * |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 144-LQFP |
| 供应商设备封装： | 144-LQFP（20x20） |
| 包装： | 托盘 |
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__________________________________________________________________________________________DS26900
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(TDO) signals can each be individually inverted by setting an optional configuration bit. Figure 1-1 diagrams this
path in a simple form.
4.3
GPIO Pins—General-Purpose I/O
The general-purpose I/O (GPIO) are bidirectional pins that offer the user the ability to output logic levels or read
input logic levels. Each GPIO pin can be configured to output logic 1, logic 0, or to be an input. Configuration of the
GPIO pins for write or read operation is accomplished by writing the GPIO Configuration and Write Register
(GPIOCR) bits.
The reading the logic state of the GPIO pins can be accomplished by accessing the 4-bit GPIO Read Register
(GPIORR). Pins that are configured for read mode read the input logic state in the register. Pins that are configured
for output mode read back the logic state for which those pins are configured.
4.4
Programmable Pullup/Pulldown Resistors
A hardware configuration pin (PREN) is provided to enable/disable pull resistors on the input signal pins of the
three masters. PREN works such that when connected to VDD, the following signals have pull resistors enabled:
TCK1, TCK2, ETDI, ETCK, TMS1, TMS2—20k
pulldown
TDI1, TDI2, ETDO, TDO1, TDO2—10k
pullup
TRST1, TRST2, ECFG, ETMS—10k
pullup
When connected to VSS, the pull resistors on the signals above are disabled. PREN can be connected to VDD for
single device implementations or for one of the devices in a multiple-device implementation. Connecting PREN to
VDD on multiple devices, which are in parallel, would cause the pull resistors to be connected in parallel. This would
have the undesirable effect of halving the pull-resistor values.
4.5
Signal Path Configuration—Inversions
To help overcome possible timing issues, the JTAG signal path timing can be modified in limited ways in the
Device Configuration Register (DCR). Signal path timing changes are global and, once set, they apply to all
secondary ports until reconfigured. Figure 1-1 diagrams the relative placement of the signal path modifier logic.
There are several possible options:
The test clock (TCK) from the arbitrated master to a slave port can be inverted by setting the TCKi bit.
The test data from the arbitrated master to a slave port can be inverted by setting the TDIi bit.
The test data coming from the slave port to the arbitrated master can be inverted by setting the TDOi bit.
The TMS signal from the arbitrated master to a slave port can be inverted by setting the TMSi bit.
There is only one set of configuration bits. Switching from port to port does not change the configuration bits.
4.6
Switch Configuration by External Test Master
The External Test Master (ETM) has the highest priority in the master arbitration circuit, so asserting
EREQ low
makes the ETM the master. The ETM accesses the configuration mode of the switch by asserting
EREQ low and
ECFG low. Access is then provided to the Switch TAP Controller. While in configuration mode, the secondary slave
ports’ JTAG signals are asserted low (except
STRSTn signals, which are high) and do not toggle. In configuration
mode, the master has access to the configuration registers in the Switch TAP Controller. When
EREQ is asserted
low and a Secondary Port Selection Register (SPSR) address from 1 to 18 is selected, the selected secondary port
JTAG signal group follows the ETM signals.
The Switch TAP Controller operates as an IEEE 1149.1 TAP controller. Instructions can be written and registers
written or read using the 1149.1 state diagram. The Switch TAP Controller uses the inverted
ECFG signal as reset.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| DS26900LN+ | 功能描述:多路器开关 IC JTAG MUX RoHS:否 制造商:Texas Instruments 通道数量:1 开关数量:4 开启电阻（最大值）:7 Ohms 开启时间（最大值）: 关闭时间（最大值）: 传播延迟时间:0.25 ns 工作电源电压:2.3 V to 3.6 V 工作电源电流: 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:UQFN-16 |
| DS26900N+ | 制造商:MAXIM 制造商全称:Maxim Integrated Products 功能描述:JTAG Multiplexer/Switch |
| DS26C31 | 制造商:NSC 制造商全称:National Semiconductor 功能描述:CMOS QUAD TRI-STATE DIFFERENTIAL LINE DRIVER |
| DS26C31 DIE | 制造商:Texas Instruments 功能描述: |
| DS26C31_BBA3026X WAF | 制造商:Texas Instruments 功能描述: |
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