参数资料
型号: DS26900LN+
厂商: Maxim Integrated Products
文件页数: 40/49页
文件大小: 0K
描述: IC JTAG MUX/SWITCH 144-LQFP
标准包装: 90
系列: *
功能: *
电压电源: 单电源
电压 - 电源,单路/双路(±): 3.14 V ~ 3.47 V
电流 - 电源: *
工作温度: *
安装类型: 表面贴装
封装/外壳: 144-LQFP
供应商设备封装: 144-LQFP(20x20)
包装: 托盘
__________________________________________________________________________________________DS26900
45
11.2 Transparent Mode Master/Slave Port Timing
Table 11-2. Master/Slave Port Timing
(VDD = 3.3V ±5%, TA = -40°C to +85°C.) (See Figure 11-2.)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
NOTES
ETCK, TCLK1, TCLK2 to STCKx Latency
ETMS, TMS1, TMS2 to STMSx Latency
ETDI, TDI1, TDI2 to STDIx Latency
t1
3
11
ns
1
ETCK, TCLK1, TCLK2 to STCKx Skew
ETMS, TMS1, TMS2 to STMSx Skew
ETDI, TDI1, TDI2 to STDIx Skew
t2
0.8
4.0
ns
2, 3
STDOx to ETDO, TDO1, TDO2 Latency
t3
3
11
ns
4
TDO + TCK
t5
11.4
16
26.4
ns
5
Note 1:
Delay (latency) from a particular master port signal to the corresponding slave port signal.
Note 2:
Skew values are with respect to a signal from the arbitrated master to the same signal on the selected secondary slave port.
Note 3:
Skew from any set of two signals at a master port to the corresponding two signals at the selected slave port.
Note 4:
Delay path from a selected slave port STDO to the arbitrated master’s TDO.
Note 5:
Half-cycle path from falling edge STCK/STDO (launch) to rising edge TCK/TDO (capture), pass-through path (see Figure 11-2).
Note 6:
TCK corresponds to each master port clock when being used to configure the core JTAG controller, e.g., ETCK or TCK1 or TCK2.
TDI, TMS correspond to the master port TDI, TMS, e.g., ETDI, ETMS or TDI1, TMS1 or TDI2, TMS2. TDO corresponds to the
master port TDO when being used to configure the core JTAG controller, e.g., ETDO or TDO1 or TDO2.
Note 7:
STCK corresponds to each slave port clock, e.g., STCK1–STCK18. STDI, STMS correspond to the slave port TDI, TMS, e.g.,
STDI1–STDI18, STMS1–STMS18. STDO corresponds to the slave port STDO1–STDO18.
Figure 11-2. Transparent Mode Master/Slave Port Timing Diagram
ETCK, TCK1, TCK2
ETMS, TMS1, TMS2
ETDI, TDI1, TDI2
STCKn, STMSn, STDIn
STDOn
ETDO, TDO1, TDO2
t5
t1
t2
t3
t4
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