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| 型号： | DS26900LN+ |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 47/49页 |
| 文件大小： | 0K |
| 描述： | IC JTAG MUX/SWITCH 144-LQFP |
| 标准包装： | 90 |
| 系列： | * |
| 功能： | * |
| 电压电源： | 单电源 |
| 电压 - 电源，单路/双路(±)： | 3.14 V ~ 3.47 V |
| 电流 - 电源： | * |
| 工作温度： | * |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 144-LQFP |
| 供应商设备封装： | 144-LQFP（20x20） |
| 包装： | 托盘 |
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__________________________________________________________________________________________DS26900
7
2. Pin Descriptions
Table 2-1. Pin Descriptions (Sorted by Function)
NAME
PIN
TYPE
FUNCTION
ETCK
4
Ipd
External Test Master Clock. In configuration mode, a falling edge on this pin clocks
data in on the ETDI pin. A falling edge on this pin clocks data out on the ETDO pin.
When PREN = VDD, a 20k pulldown resistor is connected to this pin.
ETDI
2
Ipd
External Test Master Serial Data Input. In configuration mode, data is clocked in on
this pin on the falling edge of ETCK.
When PREN = VDD, a 20k pulldown resistor is connected to this pin.
ETDO
3
O/
High
Impedance
External Test Master Serial Data Out. (High Impedance) Data is clocked out on this
pin on the falling edge of ETCK.
When PREN = VDD, a 10k pullup resistor is connected to this pin.
ECFG
5
Ipu
External Test Master Configuration (Active Low). Asserting this pin low along with
EREQ asserted low allows the External Test Master to configure the DS26900,
allowing access to the Switch TAP Controller. Toggling
ECFG when EREQ is high has
no effect.
When PREN = VDD, a 10k pullup resistor is connected to this pin.
ETMS
6
Ipu
External Test Master Test Mode Select. This pin is sampled on the rising edge of
ETCK and is used to place the port into the various defined IEEE 1149.1 states.
When PREN = VDD, a 10k pullup resistor is connected to this pin.
EREQ
1
Ipu
External Test Master Request (Active Low). (Internal 10k
Pullup) When active,
this pin selects the external test port as the master. When switching
EREQ, none of
the master clocks should be toggling.
MGNT0
144
O
Master Grant 0 (Active Low). Asserted low when the external test master is the
arbitrated master.
TCK1
22
Ipd/O
Test Master 1 Test Port Clock
Master Mode = Input
Slave Mode = Output
When PREN = VDD, an internal 20k pulldown resistor is connected to this pin.
TDI1
20
Ipu/O
Test Master 1 Test Port Serial Data Input
Master Mode = Input
Slave Mode = Output
When PREN = VDD, an internal 10k pullup resistor is connected to this pin.
TDO1
21
I/O
Test Master 1 Test Port Serial Data Out
Master Mode = Output
Slave Mode = Input
When PREN = VDD, an internal 10k pullup resistor is connected to this pin.
TRST1
23
Ipu/O
Test Master 1 Test Port Test Reset (Active Low). Asserting this pin low (when
master) puts the DS26900 into configuration mode, allowing access to the Switch
TAP Controller. Toggling
TRST1 when not the arbitrated master has no effect. This
pin does not directly affect secondary port resets.
Master Mode =
TRST1 Input
Slave Mode =
TRST1 Output
When PREN = VDD, an internal 10k pullup resistor is connected to this pin.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| DS26900LN+ | 功能描述:多路器开关 IC JTAG MUX RoHS:否 制造商:Texas Instruments 通道数量:1 开关数量:4 开启电阻（最大值）:7 Ohms 开启时间（最大值）: 关闭时间（最大值）: 传播延迟时间:0.25 ns 工作电源电压:2.3 V to 3.6 V 工作电源电流: 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:UQFN-16 |
| DS26900N+ | 制造商:MAXIM 制造商全称:Maxim Integrated Products 功能描述:JTAG Multiplexer/Switch |
| DS26C31 | 制造商:NSC 制造商全称:National Semiconductor 功能描述:CMOS QUAD TRI-STATE DIFFERENTIAL LINE DRIVER |
| DS26C31 DIE | 制造商:Texas Instruments 功能描述: |
| DS26C31_BBA3026X WAF | 制造商:Texas Instruments 功能描述: |
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