参数资料
型号: DS28E04S-100+T
厂商: Maxim Integrated Products
文件页数: 10/37页
文件大小: 0K
描述: IC EEPROM 4KBIT 16SOIC
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
格式 - 存储器: EEPROMs - 串行
存储器类型: EEPROM
存储容量: 4K (256 x 16)
接口: 1 线 串行
工作温度: -40°C ~ 85°C
封装/外壳: 16-SOIC(0.154",3.90mm 宽)
供应商设备封装: 16-SOIC
包装: 带卷 (TR)
DS28E04-100: 4096-Bit 1-Wire Addressable EEPROM with PIO
PIO Activity Latch State Register
ADDR
b7
b6
b5
b4
b3
b2
b1
b0
0222h 0 0 0 0 0 0 AL1 AL0
The data in this register represents the current state of the PIO activity latches. This register is read using the Read
Memory command. This register is read-only. Each bit is associated with the activity latch of the respective PIO
channel. Bits 2 to 7 have no function; they always read 0. A state transition on a PIO pin, High ? Low or
Low ? High, of a duration greater than t PWMIN causes the associated bit in the register to be set to a 1. This register
is cleared to 00h by a power-on reset, or by successful execution of the Reset Activity Latches command.
The next three registers control the device's participation a Conditional Search ROM sequence. The interaction of
the various signals that determine whether the device responds to a conditional search is illustrated in Figure 7.
There is a selection mask, SM, to select the participating PIOs, a polarity selection SP to specify for each channel
whether the channel signal needs to be 1 or 0 to qualify, and a PLS bit to select either the activity latches or PIO
pins as inputs. The signals of all channels are fed into an AND gate as well as an OR gate. The CT bit finally
selects the ANDed or ORed result as the conditional search response signal CSR. If CT is 0, the channel signal of
at least one of the selected channels must match the corresponding polarity. If CT is 1, the channel signals of all
selected channels must match the corresponding polarity.
Figure 7. CONDITIONAL SEARCH LOGIC
PLS
Channel 0
SP0
SM0
CT
AL0
P0
CSR
AL1
Channel 1
SP1
SM1
PORL
P1
Conditional Search Channel Selection Mask Register
ADDR
b7
b6
b5
b4
b3
b2
b1
b0
0223h 0 0 0 0 0 0 SM1 SM0
The data in this register controls whether a PIO channel qualifies for participation in the conditional search
command. To include a PIO channel, the bits in this register that correspond to those channels need to be set to 1.
This register can only be written through the Write Register command. This register is read/write. Each bit is
associated with the respective PIO channel as shown in Figure 7. Bits 2 to 7 have no function; they always read 0
and cannot be changed to 1. This register is cleared to 00h by a power-on reset.
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