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参数资料
| 型号： | DS28E04S-100+T |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 29/37页 |
| 文件大小： | 0K |
| 描述： | IC EEPROM 4KBIT 16SOIC |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 2,500 |
| 格式 - 存储器： | EEPROMs - 串行 |
| 存储器类型： | EEPROM |
| 存储容量： | 4K (256 x 16) |
| 接口： | 1 线 串行 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 16-SOIC（0.154"，3.90mm 宽） |
| 供应商设备封装： | 16-SOIC |
| 包装： | 带卷 (TR) |
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DS28E04-100: 4096-Bit 1-Wire Addressable EEPROM with PIO
Master-to-Slave
For a write-one time slot, the voltage on the data line must have crossed the V TH threshold before the write-one
low time t W1LMAX is expired. For a write-zero time slot, the voltage on the data line must stay below the V TH
threshold until the write-zero low time t W0LMIN is expired. For the most reliable communication, the voltage on the
data line should not exceed V ILMAX during the entire t W0L or t W1L window. After the V TH threshold has been crossed,
the DS28E04-100 needs a recovery time t REC before it is ready for the next time slot.
Slave-to-Master
A read-data time slot begins like a write-one time slot. The voltage on the data line must remain below V TL until the
read low time t RL is expired. During the t RL window, when responding with a 0, the DS28E04-100 starts pulling the
data line low; its internal timing generator determines when this pulldown ends and the voltage starts rising again.
When responding with a 1, the DS28E04-100 does not hold the data line low at all, and the voltage starts rising as
soon as t RL is over.
The sum of t RL + δ (rise time) on one side and the internal timing generator of the DS28E04-100 on the other side
define the master sampling window (t MSRMIN to t MSRMAX ) in which the master must perform a read from the data line.
For the most reliable communication, t RL should be as short as permissible, and the master should read close to
but no later than t MSRMAX . After reading from the data line, the master must wait until t SLOT is expired. This
guarantees sufficient recovery time t REC for the DS28E04-100 to get ready for the next time slot. Note that t REC
specified herein applies only to a single DS28E04-100 attached to a 1-Wire line. For multidevice configurations,
t REC needs to be extended to accommodate the additional 1-Wire device input capacitance. Alternatively, an
interface that performs active pullup during the 1-Wire recovery time such as the DS2482-x00 or DS2480B 1-Wire
line drivers can be used.
IMPROVED NETWORK BEHAVIOR (SWITCHPOINT HYSTERESIS)
In a 1-Wire environment, line termination is possible only during transients controlled by the bus master (1-Wire
driver). 1-Wire networks, therefore, are susceptible to noise of various origins. Depending on the physical size and
topology of the network, reflections from end points and branch points can add up, or cancel each other to some
extent. Such reflections are visible as glitches or ringing on the 1-Wire communication line. Noise coupled onto the
1-Wire line from external sources can also result in signal glitching. A glitch during the rising edge of a time slot can
cause a slave device to lose synchronization with the master and, consequently, result in a search ROM command
coming to a dead end or cause a device-specific function command to abort. For better performance in network
applications, the DS28E04-100 uses a new 1-Wire front end, which makes it less sensitive to noise and also
reduces the magnitude of noise injected by the slave device itself.
The 1-Wire front end of the DS28E04-100 differs from traditional slave devices in four characteristics.
1) The falling edge of the presence pulse has a controlled slew rate. This provides a better match to the line
impedance than a digitally switched transistor, converting the high-frequency ringing known from traditional
devices into a smoother low-bandwidth transition. The slew-rate control is specified by the parameter t FPD ,
which has different values for standard and Overdrive speed.
2) There is additional lowpass filtering in the circuit that detects the falling edge at the beginning of a time slot.
This reduces the sensitivity to high-frequency noise. This additional filtering does not apply at Overdrive speed.
3) There is a hysteresis at the low-to-high switching threshold V TH . If a negative glitch crosses V TH but does not go
below V TH - V HY , it will not be recognized (Figure 17, Case A). The hysteresis is effective at any 1-Wire speed.
4) There is a time window specified by the rising edge hold-off time t REH during which glitches are ignored, even if
they extend below V TH - V HY threshold (Figure 17, Case B, t GL < t REH ). Deep voltage droops or glitches that
appear late after crossing the V TH threshold and extend beyond the t REH window cannot be filtered out and are
taken as the beginning of a new time slot (Figure 17, Case C, t GL ≥ t REH ).
Only devices that have the parameters t FPD , V HY , and t REH specified in their electrical characteristics use the
improved 1-Wire front end.
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相关代理商/技术参数 |
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| DS28E04S-224-BB+T | 制造商:Maxim Integrated Products 功能描述:- Tape and Reel |
| DS28E05P+ | 功能描述:电可擦除可编程只读存储器 1W 1KB FTP MEMORY TSOC RoHS:否 制造商:Atmel 存储容量:2 Kbit 组织:256 B x 8 数据保留:100 yr 最大时钟频率:1000 KHz 最大工作电流:6 uA 工作电源电压:1.7 V to 5.5 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:SOIC-8 |
| DS28E05P+T | 功能描述:电可擦除可编程只读存储器 1W 1KB FTP MEMORY TSOC RoHS:否 制造商:Atmel 存储容量:2 Kbit 组织:256 B x 8 数据保留:100 yr 最大时钟频率:1000 KHz 最大工作电流:6 uA 工作电源电压:1.7 V to 5.5 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:SOIC-8 |
| DS28E05R+T | 功能描述:电可擦除可编程只读存储器 1-Wire 112-BYTE 电可擦除可编程只读存储器 RoHS:否 制造商:Atmel 存储容量:2 Kbit 组织:256 B x 8 数据保留:100 yr 最大时钟频率:1000 KHz 最大工作电流:6 uA 工作电源电压:1.7 V to 5.5 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:SOIC-8 |
| DS28E10 | 制造商:MAXIM 制造商全称:Maxim Integrated Products 功能描述:1-Wire SHA-1 Authenticator Irreversible Write Protection |
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