参数资料
| 型号： | DS3120N |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 126/133页 |
| 文件大小： | 0K |
| 描述： | IC FRAMER T1 28-CHANNEL IND |
| 标准包装： | 1 |
| 控制器类型： | T1 调帧器 |
| 接口： | 并行/串行 |
| 电源电压： | 2.97 V ~ 3.63 V |
| 电流 - 电源： | 300mA |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 316-BGA |
| 包装： | 管件 |
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DS3112
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Bit 6: Receive Packet End (RPE). This latched read-only event-status bit will be set to a one each time the HDLC
controller detects the finish of a message whether the packet is valid (CRC correct) or not (bad CRC, abort
sequence detected, packet too small, not an integral number of octets, or an overrun occurred). This bit will be
cleared when read and will not be set again until another message end is detected. The setting of this bit can cause a
hardware interrupt to occur if the RPE bit in the Interrupt Mask for HSR (IHSR) register is set to a one and the
HDLC bit in the Interrupt Mask for MSR (IMSR) register is set to a one. The interrupt will be allowed to clear
when this bit is read.
Bit 4: Receive FIFO High Watermark (RHWM). This read-only real-time status bit will be set to a one when the
receive FIFO contains more than the number of bytes configured by the Receive High Watermark Setting control
bits (RHWMS0 to RHWMS2) in the HDLC Control Register (HCR). This bit will be cleared when the FIFO
empties below the high watermark. The setting of this bit can cause a hardware interrupt to occur if the RHWM bit
in the Interrupt Mask for HSR (IHSR) register is set to a one and the HDLC bit in the Interrupt Mask for MSR
(IMSR) register is set to a one.
Bit 5: Receive Packet Start (RPS). This latched read-only event-status bit will be set to a one each time the
HDLC controller detects an opening byte of an HDLC packet. This bit will be cleared when read and will not be set
again until another message is detected. The setting of this bit can cause a hardware interrupt to occur if the RPS bit
in the Interrupt Mask for HSR (IHSR) register is set to a one and the HDLC bit in the Interrupt Mask for MSR
(IMSR) register is set to a one. The interrupt will be allowed to clear when this bit is read.
Bit 7: Transmit FIFO Underrun (TUDR). This latched read-only event-status bit will be set to a one each time
the transmit FIFO underruns and an abort is automatically sent. This bit will be cleared when read and will not be
set again until another underrun occurs (i.e., the FIFO has been written to and then allowed to empty again). The
setting of this bit can cause a hardware interrupt to occur if the TUDR bit in the Interrupt Mask for HSR (IHSR)
register is set to a one and the HDLC bit in the Interrupt Mask for MSR (IMSR) register is set to a one. The
interrupt will be allowed to clear when this bit is read.
Bits 8 to 11: Transmit FIFO Level Bits 0 to 3 (TFL0 to TFL3). These read-only real-time status bits indicate the
current depth of the transmit FIFO with a 16-byte resolution. These status bits cannot cause a hardware interrupt.
TFL3
TFL2
TFL1
TFL0
TRANSMIT FIFO LEVEL
0
empty to 15 bytes
0
1
16 to 31 bytes
0
1
0
32 to 47 bytes
0
1
48 to 63 bytes
0
1
0
64 to 79 bytes
0
1
0
1
80 to 95 bytes
0
1
0
96 to 111 bytes
0
1
112 to 127 bytes
1
0
128 to 143 bytes
1
0
1
144 to 159 bytes
1
0
1
0
160 to 175 bytes
1
0
1
176 to 191 bytes
1
0
192 to 207 bytes
1
0
1
208 to 223 bytes
1
0
224 to 239 bytes
1
240 to 256 bytes
Bit 12: Transmit FIFO Empty (TEMPTY). This read-only real-time status bit will be set to a one when the
transmit FIFO is empty. It will be cleared when the transmit FIFO contains one or more bytes. This status bit
cannot cause a hardware interrupt.
Bit 13: Receive FIFO Overrun (ROVR). This latched read-only event-status bit will be set to a one each time the
receive FIFO overruns. This bit will be cleared when read and will not be set again until another overrun occurs
相关PDF资料 |
PDF描述 |
|---|---|
| DS31256+ | IC CTRLR HDLC 256-CHANNEL 256BGA |
| DS3141+ | IC FRAMER DS3/E3 SNGL 144CSBGA |
| DS31412N | IC 12CH DS3/3 FRAMER 349-BGA |
| DS3150TN | IC LIU T3/E3/STS-1 IND 48-TQFP |
| DS3154N+ | IC LIU DS3/E3/STS-1 QD 144CSBGA |
相关代理商/技术参数 |
参数描述 |
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| DS3121 | 功能描述:IC TGATOR T1-T3 AGGREGATOR RoHS:否 类别:集成电路 (IC) >> 接口 - 控制器 系列:- 标准包装:4,900 系列:- 控制器类型:USB 2.0 控制器 接口:串行 电源电压:3 V ~ 3.6 V 电流 - 电源:135mA 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:36-VFQFN 裸露焊盘 供应商设备封装:36-QFN（6x6） 包装:* 其它名称:Q6396337A |
| DS3121N | 功能描述:IC TGATOR T1-T3 AGGREGATOR IND RoHS:否 类别:集成电路 (IC) >> 接口 - 控制器 系列:- 标准包装:4,900 系列:- 控制器类型:USB 2.0 控制器 接口:串行 电源电压:3 V ~ 3.6 V 电流 - 电源:135mA 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:36-VFQFN 裸露焊盘 供应商设备封装:36-QFN（6x6） 包装:* 其它名称:Q6396337A |
| DS31256 | 功能描述:输入/输出控制器接口集成电路 256Ch High Thruput HDLC Cntlr RoHS:否 制造商:Silicon Labs 产品: 输入/输出端数量: 工作电源电压: 最大工作温度:+ 85 C 最小工作温度:- 40 C 安装风格:SMD/SMT 封装 / 箱体:QFN-64 封装:Tray |
| DS31256+ | 功能描述:输入/输出控制器接口集成电路 256Ch High Thruput HDLC Cntlr RoHS:否 制造商:Silicon Labs 产品: 输入/输出端数量: 工作电源电压: 最大工作温度:+ 85 C 最小工作温度:- 40 C 安装风格:SMD/SMT 封装 / 箱体:QFN-64 封装:Tray |
| DS31256B | 功能描述:输入/输出控制器接口集成电路 256Ch High Thruput HDLC Cntlr RoHS:否 制造商:Silicon Labs 产品: 输入/输出端数量: 工作电源电压: 最大工作温度:+ 85 C 最小工作温度:- 40 C 安装风格:SMD/SMT 封装 / 箱体:QFN-64 封装:Tray |
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