- 您现在的位置：买卖IC网 > PDF目录10993 > DS3170N+ (Maxim Integrated Products)IC TXRX DS3/E3 100-CSBGA PDF资料下载
参数资料
| 型号： | DS3170N+ |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 224/230页 |
| 文件大小： | 0K |
| 描述： | IC TXRX DS3/E3 100-CSBGA |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 640 |
| 功能： | 单芯片收发器 |
| 接口： | DS3，E3 |
| 电路数： | 1 |
| 电源电压： | 3.135 V ~ 3.465 V |
| 电流 - 电源： | 120mA |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 100-LBGA，CSBGA |
| 供应商设备封装： | 100-CSBGA（11x11） |
| 包装： | 托盘 |
| 包括： | DS3 调帧器，E3 调帧器，HDLC 控制器，芯片内 BERT |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页第81页第82页第83页第84页第85页第86页第87页第88页第89页第90页第91页第92页第93页第94页第95页第96页第97页第98页第99页第100页第101页第102页第103页第104页第105页第106页第107页第108页第109页第110页第111页第112页第113页第114页第115页第116页第117页第118页第119页第120页第121页第122页第123页第124页第125页第126页第127页第128页第129页第130页第131页第132页第133页第134页第135页第136页第137页第138页第139页第140页第141页第142页第143页第144页第145页第146页第147页第148页第149页第150页第151页第152页第153页第154页第155页第156页第157页第158页第159页第160页第161页第162页第163页第164页第165页第166页第167页第168页第169页第170页第171页第172页第173页第174页第175页第176页第177页第178页第179页第180页第181页第182页第183页第184页第185页第186页第187页第188页第189页第190页第191页第192页第193页第194页第195页第196页第197页第198页第199页第200页第201页第202页第203页第204页第205页第206页第207页第208页第209页第210页第211页第212页第213页第214页第215页第216页第217页第218页第219页第220页第221页第222页第223页当前第224页第225页第226页第227页第228页第229页第230页
DS3170 DS3/E3 Single-Chip Transceiver
93 of 230
FA1 and FA2 are the Frame Alignment bytes. EM is the Error Monitoring byte used for path error monitoring. TR is
the Trail Trace byte used for end-to-end connectivity verification. MA is the Maintenance and Adaptation byte used
for far-end path status and performance monitoring.
NR is the Network Operator byte allocated for network operator maintenance purposes. GC is the General Purpose
Communications Channel byte allocated for user communications purposes.
10.6.8.2
Transmit G.832 E3 Frame Generation
G.832 E3 frame generation receives the incoming payload data stream, and overwrites all of the E3 overhead byte
locations.
The first two bytes of the first row in the frame are overwritten with the frame alignment bytes FA1 and FA2, which
have a value of F6h and 28h respectively.
The first byte in the second row of the frame is overwritten with the EM byte which is a BIP-8 calculated over all of
the bytes of the previous frame after all frame processing (frame generation, error insertion, overhead insertion,
and AIS generation) has been performed. The first byte in the third row of the frame is overwritten with the TR byte
which is input from the transmit trail trace controller.
The first byte in the fourth row of the frame is overwritten with the MA byte (see Figure 10-18), which consists of the
RDI bit, REI bit, payload type, multiframe indicator, and timing source indicator.
The RDI bit can be generated automatically, set to one, or set to zero. The RDI source is programmable
(automatic, 1, or 0). If the RDI is generated automatically, it is set to one when one or more of the indicated alarm
conditions is present, and set to zero when all of the indicated alarm conditions are absent. Automatically setting
RDI on LOS, LOF, or AIS is individually programmable (on or off).
The REI bit can be generated automatically or inserted from a register bit. The REI source is programmable
(automatic or register). If REI is generated automatically, it is one when at least one parity error has been detected
during the previous frame.
The payload type is sourced from a register. The three register bits are inserted in the third, fourth, and fifth bits of
the MA byte in each frame.
The multiframe indicator and timing marker bits can be directly inserted from a 3-bit register or generated from a 4-
bit register. The multiframe indicator and timing marker insertion type is programmable (direct or generated). When
the multiframe indicator and timing marker bits are directly inserted, the three register bits are inserted in the last
three bits of the MA byte in each frame. When the multiframe indicator and timing marker bits are generated, the
four timing source indicator bits are transferred in a four-frame multiframe, MSB first. The multiframe indicator bits
(sixth and seventh bits of the MA byte) identify the phase of the multiframe (00, 01, 10, or 11), and the timing
marker bit (eighth bit of the MA byte) contains the corresponding timing source indicator bit (TMABR register bits
TTI3, TTI2, TTI1, or TTI0 respectively). Note: The initial phase of the multiframe is arbitrarily chosen.
The first byte in the fifth row of the frame is overwritten with the NR byte which can be sourced from a register, from
the transmit FEAC controller, or from the transmit HDLC controller. The NR byte source is programmable (register,
FEAC, or HDLC). Note: The HDLC controller will source eight bits per frame period regardless of whether the NR
byte only, GC byte only, or both are programmed to be sourced from the HDLC controller.
The first byte in the sixth row of the frame is overwritten with the GC byte which can be sourced from a register or
from the transmit HDLC controller. The GC byte source is programmable (register or HDLC).
Once all of the E3 overhead bytes have been overwritten, the data stream is passed on to error insertion. If frame
generation is disabled, the incoming E3 signal is passed on directly to error insertion. Frame generation is
programmable (on or off).
10.6.8.3
Transmit G.832 E3 Error Insertion
Error insertion inserts various types of errors into the different E3 overhead bytes. The types of errors that can be
inserted are framing errors, BIP-8 parity errors, and Remote Error Indication (REI) errors.
The type of framing error(s) inserted is programmable (errored frame alignment bit or errored frame alignment
word). A frame alignment bit error is a single bit error in the frame alignment word (FA1 or FA2). A frame alignment
word error is an error in all sixteen bits of the frame alignment word (the values 09h and D7h are inserted in the
FA1 and FA2 bytes respectively). Framing error(s) can be inserted one error at a time, or four consecutive frames.
The framing error insertion mode (single or four) is programmable.
相关PDF资料 |
PDF描述 |
|---|---|
| DS2151QB | IC TXRX T1 1-CHIP 5V LP 44-PLCC |
| DS21Q58LN+ | IC TXRX E1 QUAD 3.3V 100LQFP |
| DS26504LN+ | IC T1/E1/J1 64KCC ELEMENT 64LQFP |
| DS21352G | IC TXRX T1 1-CHIP 3.3V 100-BGA |
| DS2174QN+T&R | IC BERT ENHANCED 44-PLCC |
相关代理商/技术参数 |
参数描述 |
|---|---|
| DS3170N+ | 功能描述:网络控制器与处理器 IC DS3/E3 Single-Chip Transceiver RoHS:否 制造商:Micrel 产品:Controller Area Network (CAN) 收发器数量: 数据速率: 电源电流（最大值）:595 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:PBGA-400 封装:Tray |
| DS3170N+T&R | 制造商:Maxim Integrated Products 功能描述:SINGLE PORT DS3/E3 SCT T&R IND LF - Tape and Reel 制造商:Maxim Integrated Products 功能描述:IC TXRX DS3/E3 100CSBGA |
| DS3170N+T&R | 功能描述:网络控制器与处理器 IC DS3/E3 Single-Chip Transceiver RoHS:否 制造商:Micrel 产品:Controller Area Network (CAN) 收发器数量: 数据速率: 电源电流（最大值）:595 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:PBGA-400 封装:Tray |
| DS3171 | 功能描述:网络控制器与处理器 IC Single DS3/E3 Single Chip Transceiver RoHS:否 制造商:Micrel 产品:Controller Area Network (CAN) 收发器数量: 数据速率: 电源电流（最大值）:595 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:PBGA-400 封装:Tray |
| DS3171N | 功能描述:网络控制器与处理器 IC Single DS3/E3 Single Chip Transceiver RoHS:否 制造商:Micrel 产品:Controller Area Network (CAN) 收发器数量: 数据速率: 电源电流（最大值）:595 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:PBGA-400 封装:Tray |
发布紧急采购，3分钟左右您将得到回复。