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| 型号： | EM250-RCM-R |
| 厂商： | Silicon Laboratories Inc |
| 文件页数： | 101/124页 |
| 文件大小： | 0K |
| 描述： | EM250 RCM BOARD |
| 标准包装： | 12 |
| 类型： | 收发器，802.15.4/Zigbee |
| 频率： | 2.4GHz |
| 适用于相关产品： | EM250 |
| 其它名称： | 636-1023 |
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EM250
5.6
Event Manager
The XAP2b core supports one IRQ and one wake-up input; however, the EM250 contains an advanced Event
Manager that takes IRQ and WAKE_UP signals from a variety of internal and external sources and provides
them to the XAP2b. The Event Manager allows for each event to be separately masked and cleared by the
CPU, and ensures that all events are serviced properly and promptly.
IRQ event sources include:
?
?
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?
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Timer events
GPIO events
SC1 and SC2 events
ADC
System-mode sources (MAC, Watchdog, etc.)
WAKE_UP event sources include:
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?
?
?
Timer events
GPIO events
SC1 and SC2 events
System-mode sources (MAC, Watchdog, etc.)
All interrupt source signals (except level-triggered GPIO interrupt signals) are momentary pulses that are
guaranteed to be a single cycle of the main 12MHz clock. They will synchronously set the corresponding
interrupt source bit(s) within a set of hierarchically organized interrupt source register(s). The interrupt
controller merges these hierarchical interrupt sources into the single interrupt input to the CPU. Table 37
illustrates the enable and configuration status of each event within the EM250.
Table 37. Event Enable and Configuration Status
2 : INT_periphFLAG
Event
Interrupt pin to CPU
Top: INT_FLAG
nd
Configuration
INT_EN
INT_CFG
INT_periphCFG
The hierarchy has two levels of interrupt source and associated mask registers for fine control of interrupt
processing. The top-level INT_FLAG and INT_CFG registers have one bit per major functional module of the
EM250. The second level is a set of INT_periphFLAG and INT_periphCFG registers that each have one bit per
sub-function within their respective module. Some modules, like ADC, have no second level. For a top-level
event to actually interrupt the CPU, it must be enabled in the top-level INT_CFG register. Second-level events
must additionally be enabled in their respective second-level INT_periphCFG registers.
To clear (acknowledge) an interrupt, software must write a 1 into the corresponding bit of the interrupt's
lowest level INT_periphFLAG register. For example, to acknowledge an ADC interrupt, which has no second
level, software must write a 1 into the INT_ADC bit of the top-level INT_FLAG register. To acknowledge a SC1
RXVALID second-level interrupt, software must write a 1 into the INT_SCRXVAL bit of the second-level
INT_SC1FLAG register. If there were other enabled SC1 interrupts pending, the top-level INT_SC1 bit in the
INT_FLAG register would remain set, representing the “or” of all second-level-enabled SC1 interrupt events.
The interrupt source register bits are designed to remain set if the event reoccurs at the same moment the bit
is being cleared to acknowledge a prior occurrence.
If another enabled interrupt of the same type occurs before being acknowledged by the software ISR, it will
be lost because no counting or queuing is used. However, this condition is detected and stored in the top-level
INT_MISS register to facilitate software detection of such problems. The INT_MISS register is
Page 101
120-0082-000V Rev 1.1
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相关代理商/技术参数 |
参数描述 |
|---|---|
| EM250-RTR | 功能描述:IC ZIGBEE SYSTEM-ON-CHIP 48-QFN RoHS:是 类别:RF/IF 和 RFID >> RF 收发器 系列:EM250 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:30 系列:- 频率:4.9GHz ~ 5.9GHz 数据传输率 - 最大:54Mbps 调制或协议:* 应用:* 功率 - 输出:-3dBm 灵敏度:- 电源电压:2.7 V ~ 3.6 V 电流 - 接收:* 电流 - 传输:* 数据接口:PCB，表面贴装 存储容量:- 天线连接器:PCB，表面贴装 工作温度:-25°C ~ 85°C 封装/外壳:68-TQFN 裸露焊盘 包装:管件 |
| EM250-STACK-R | 制造商:Silicon Laboratories Inc 功能描述:EM250 BOARD STACK (RCM + BREAKOUT) - Boxed Product (Development Kits) 制造商:Silicon Laboratories Inc 功能描述:BOARD STACK EM250 RCM & BREAKOUT |
| EM25-12V-DC | 制造商:ECLIPSE MAGNETICS 功能描述:HOLDING ELECTRO MAGNET |
| EM2513N/11560 | 制造商:ebm-papst Inc 功能描述:- Bulk |
| EM2524N/11560 | 制造商:ebm-papst Inc 功能描述:- Bulk |
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