参数资料
型号: EM250-RCM-R
厂商: Silicon Laboratories Inc
文件页数: 47/124页
文件大小: 0K
描述: EM250 RCM BOARD
标准包装: 12
类型: 收发器,802.15.4/Zigbee
频率: 2.4GHz
适用于相关产品: EM250
其它名称: 636-1023
EM250
Full I 2 C frames have to be constructed under software control by generating individual I 2 C segments. All
necessary segment transitions are shown in Figure 7. ACK or NACK generation of an I 2 C receive frame segment
is determined with the register bit SC_I2CACK in the SC1_I2CCTRL2 register.
IDLE
START Segment
STOP Segment
RECEIVE Segment
with NACK
NO
TRANSMIT Segment
received ACK ?
YES
RECEIVE Segment
with ACK
Figure 7. I2C Segment Transitions
Generation of a 7-bit address is accomplished with one transmit segment. The upper 7 bits of the transmitted
character contain the 7-bit address. The remaining lower bit contains the command type (“read” or “write”).
Generation of a 10-bit address is accomplished with two transmit segments. The upper 5 bits of the first
transmit character must be set to 0x1E . The next 2 bits are for the 2 most significant bits of the 10-bit
address. The remaining lower bit contains the command type (“read” or “write”). The second transmit
segment is for the remaining 8 bits of the 10-bit address.
Characters received and transmitted are passed through receive and transmit FIFOs. The SC1 I 2 C master
transmit and receive FIFOs are 1-byte deep. These FIFOs are accessed under software control.
(Re)start and stop segments are initiated by setting the register bits SC_I2CSTART or SC_I2CSTOP in the
SC1_I2CCTRL1 register followed by waiting until they have cleared. Alternatively, the register bit
SC_I2CCMDFIN in the SC1_I2CSTAT can be used for waiting.
To initiate a transmit segment, the data have to be written to the SC1_DATA data register, followed by setting
the register bit SC_I2CSEND in the SC1_I2CCTRL1 register, and completed by waiting until it clears.
Alternatively, the register bit SC_I2CTXFIN in the SC1_I2CSTAT can be used for waiting.
A receive segment is initiated by setting the register bit SC_I2CRECV in the SC1_I2CCTRL1 register, waiting
until it clears, and then reading from the SC1_DATA data register. Alternatively, the register bit SC_I2CRXFIN
in the SC1_I2CSTAT can be used for waiting. Now the register bit SC_I2CRXNAK in the SC1_I2CSTAT register
indicates if a NACK or ACK was received from an I 2 C slave device.
Interrupts are generated on the following events:
?
?
Bus command ( SC_I2CSTART/SC_I2CSTOP ) completed (0 to 1 transition of SC_I2CCMDFIN )
Character transmitted and slave device responded with NACK
Page 47
120-0082-000V Rev 1.1
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