参数资料
型号: EM250-RCM-R
厂商: Silicon Laboratories Inc
文件页数: 53/124页
文件大小: 0K
描述: EM250 RCM BOARD
标准包装: 12
类型: 收发器,802.15.4/Zigbee
频率: 2.4GHz
适用于相关产品: EM250
其它名称: 636-1023
EM250
SC1_I2CSTAT [0x44A2]
15
0-R
0
0
0-R
7
14
0-R
0
0
0-R
6
13
0-R
0
0
0-R
5
12
0-R
0
0
0-R
4
11
0-R
0
SC_I2CCMDFIN
0-R
3
10
0-R
0
SC_I2CRXFIN
0-R
2
9
0-R
0
SC_I2CTXFIN
0-R
1
8
0-R
0
SC_I2CRXNAK
0-R
0
SC_I2CCMDFIN
SC_I2CRXFIN
SC_I2CTXFIN
SC_I2CRXNAK
[3]
[2]
[1]
[0]
This bit is set when a START or STOP command completes. It autoclears on next bus activity.
This bit is set when a byte is received. It autoclears on next bus activity.
This bit is set when a byte is transmitted. It autoclears on next bus activity.
This bit is set when a NACK is received from the slave. It autoclears on next bus activity.
SC1_DMACTRL [0x4498]
15
0-R
0
0
0-R
7
14
0-R
0
0
0-R
6
13
0-R
0
SC_TXDMARST
0-W
5
12
0-R
0
SC_RXDMARST
0-W
4
11
0-R
0
SC_TXLODB
0-RW
3
10
0-R
0
SC_TXLODA
0-RW
2
9
0-R
0
SC_RXLODB
0-RW
1
8
0-R
0
SC_RXLODA
0-RW
0
SC_TXDMARST
SC_RXDMARST
SC_TXLODB
SC_TXLODA
SC_RXLODB
SC_RXLODA
[5]
[4]
[3]
[2]
[1]
[0]
Setting this bit will reset the transmit DMA. The bit is autocleared.
Setting this bit will reset the receive DMA. This bit is autocleared.
Setting this bit loads DMA transmit buffer B addresses and starts the DMA controller processing
transmit buffer B. This bit is autocleared when DMA completes. Writing a zero to this bit will
not have any effect. Reading this bit as one indicates DMA processing for buffer B is active or
pending. Reading this bit as zero indicates DMA processing for buffer B is complete or idle.
Setting this bit loads DMA transmit buffer A addresses and starts the DMA controller processing
transmit buffer A. This bit is autocleared when DMA completes. Writing a zero to this bit will
not have any effect. Reading this bit as one indicates DMA processing for buffer A is active or
pending. Reading this bit as zero indicates DMA processing for buffer A is complete or idle.
Setting this bit loads DMA receive buffer B addresses and starts the DMA controller processing
receive buffer B. This bit is autocleared when DMA completes. Writing a zero to this bit will
not have any effect. Reading this bit as one indicates DMA processing for buffer B is active or
pending. Reading this bit as zero indicates DMA processing for buffer B is complete or idle.
Setting this bit loads DMA receive buffer A addresses and starts the DMA controller processing
receive buffer A. This bit is autocleared when DMA completes. Writing a zero to this bit will
not have any effect. Reading this bit as one indicates DMA processing for buffer A is active or
pending. Reading this bit as zero indicates DMA processing for buffer A is complete or idle.
Page 53
120-0082-000V Rev 1.1
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