参数资料
型号: EM250-RCM-R
厂商: Silicon Laboratories Inc
文件页数: 88/124页
文件大小: 0K
描述: EM250 RCM BOARD
标准包装: 12
类型: 收发器,802.15.4/Zigbee
频率: 2.4GHz
适用于相关产品: EM250
其它名称: 636-1023
EM250
5.4.5
Timer Interrupt Sources
Each timer supports a number of interrupts sources:
?
?
?
?
On overflow during up-count from all 1s to zero.
On counter reaching output compare values stored in the TMR1_CMPA , TMR1_CMPB or TMR2_CMPA , and
TMR2_CMPB registers.
On counter reaching zero, TMR1_TOP , or TMR2_TOP .
On capturing events from GPIO.
To generate interrupts to the CPU, the interrupt masks in the INT_TMRCFG and INT_CFG registers must be
enabled.
5.4.6
TMR1_CFG [0x450C]
Registers
15
0-R
0
14
0-R
0
13
0-R
0
12
0-RW
TMR_EXTEN
11
0-RW
TMR_EN
10
0-RW
TMR_BIDIR
9
0-RW
TMR_DOWN
8
0-RW
TMR_1SHOT
TMR_PSCL
TMR_FILT
TMR_EDGE
TMR_CLK
0-RW
7
0-RW
6
0-RW
5
0-RW
4
0-RW
3
0-RW
2
0-RW
1
0-RW
0
TMR_EXTEN
TMR_EN
TMR_BIDIR
TMR_DOWN
TMR_1SHOT
TMR_PSCL
TMR_FILT
TMR_EDGE
TMR_CLK
120-0082-000V Rev 1.1
[12]
[11]
[10]
[9]
[8]
[7:4]
[3]
[2]
[1:0]
Control bit for the external enable mask on a pin. When this bit is clear, do not check
status of the TMR1ENMSK pin. When this bit is set, check status of the TMR1ENMSK pin.
Set this bit to enable counting. To change other register bits, this bit must be cleared.
Set this bit to enable bi-directional alternation mode.
Initial count direction after enabling the timer. Clear this bit to count up; set this bit to
count down.
Clear this bit for auto repetition mode. Set this bit for a single shot.
Clock divider setting (N). The possible clock divisors are: 0 - 2^N (N=0..10).
Set this bit to enable clock source glitch filtering.
Clock source edge selection. Clear this bit for rising edge; set this bit for falling edge.
Clock source selection: 0 = calibrated RC oscillator (default); 1 = 32kHz; 2 = 12MHz; 3 =
External (GPIO).
Page 88
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