参数资料
型号: EP20K100
厂商: Altera Corporation
英文描述: Programmable Logic Device Family
中文描述: 可编程逻辑器件系列
文件页数: 2/117页
文件大小: 570K
代理商: EP20K100
2
Altera Corporation
APEX 20K Programmable Logic Device Family Data Sheet
Note to
Tables 1
and
2
:
(1)
The embedded IEEE Std. 1149.1 Joint Test Action Group (JTAG) boundary-scan circuitry contributes up to
57,000 additional gates.
Additional
Features
Designed for low-power operation
1.8-V and 2.5-V supply voltage (see
Table 3
)
MultiVolt
TM
I/O interface support to interface with 1.8-V, 2.5-V,
3.3-V, and 5.0-V devices (see
Table 3
)
ESB offering programmable power-saving mode
Note to
Table 3
:
(1)
APEX 20KE devices can be 5.0-V tolerant by using an external resistor.
Table 2. Additional APEX 20K Device Features
Note (1)
Feature
EP20K300E
EP20K400
EP20K400E
EP20K600E
EP20K1000E
EP20K1500E
Maximum system
gates
Typical gates
LEs
ESBs
Maximum
RAM bits
Maximum
macrocells
Maximum user I/O
pins
728,000
1,052,000
1,052,000
1,537,000
1,772,000
2,392,000
300,000
11,520
72
147,456
400,000
16,640
104
212,992
400,000
16,640
104
212,992
600,000
24,320
152
311,296
1,000,000
38,400
160
327,680
1,500,000
51,840
216
442,368
1,152
1,664
1,664
2,432
2,560
3,456
408
502
488
588
708
808
Table 3. APEX 20K Supply Voltages
Feature
Device
EP20K100
EP20K200
EP20K400
EP20K30E
EP20K60E
EP20K100E
EP20K160E
EP20K200E
EP20K300E
EP20K400E
EP20K600E
EP20K1000E
EP20K1500E
Internal supply voltage (V
CCINT
)
MultiVolt I/O interface voltage levels (V
CCIO
) 2.5 V, 3.3 V, 5.0 V
2.5 V
1.8 V
1.8 V, 2.5 V, 3.3 V, 5.0 V
(1)
相关PDF资料
PDF描述
EP20K1000E Programmable Logic Device Family
EP20K100E Programmable Logic Device Family
EP20K1500E Programmable Logic Device Family
EP20K160E Programmable Logic Device Family
EP20K200 Programmable Logic Device Family
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