参数资料
型号: EP20K100
厂商: Altera Corporation
英文描述: Programmable Logic Device Family
中文描述: 可编程逻辑器件系列
文件页数: 28/117页
文件大小: 570K
代理商: EP20K100
28
Altera Corporation
APEX 20K Programmable Logic Device Family Data Sheet
The programmable register also supports an asynchronous clear function.
Within the ESB, two asynchronous clears are generated from global
signals and the local interconnect. Each macrocell can either choose
between the two asynchronous clear signals or choose to not be cleared.
Either of the two clear signals can be inverted within the ESB.
Figure 15
shows the ESB control logic when implementing product-terms.
Figure 15. ESB Product-Term Mode Control Logic
Note to
Figure 15
:
(1)
APEX 20KE devices have four dedicated clocks.
Parallel Expanders
Parallel expanders are unused product terms that can be allocated to a
neighboring macrocell to implement fast, complex logic functions.
Parallel expanders allow up to 32 product terms to feed the macrocell
OR
logic directly, with two product terms provided by the macrocell and 30
parallel expanders provided by the neighboring macrocells in the ESB.
The Quartus II software Compiler can allocate up to 15 sets of up to two
parallel expanders per set to the macrocells automatically. Each set of two
parallel expanders incurs a small, incremental timing delay.
Figure 16
shows the APEX 20K parallel expanders.
CLK2
CLKENA2
CLK1
CLKENA1 CLR2
CLR1
Dedicated
Clocks
Global
Signals
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
2 or 4 (1)
4
相关PDF资料
PDF描述
EP20K1000E Programmable Logic Device Family
EP20K100E Programmable Logic Device Family
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