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参数资料
型号： EP20K100
厂商： Altera Corporation
英文描述： Programmable Logic Device Family
中文描述： 可编程逻辑器件系列
文件页数： 74/117页
文件大小： 570K
代理商： EP20K100
74
Altera Corporation
APEX 20K Programmable Logic Device Family Data Sheet
Note to
Tables 32
and
33
:
(1)
These timing parameters are sample-tested only.
Tables 34
through
37
show APEX 20KE LE, ESB, routing, and functional
timing microparameters for the
f
MAX
timing model.
Table 34. APEX 20KE LE Timing Microparameters
Symbol
Parameter
t
SU
t
H
t
CO
t
LUT
LE register setup time before clock
LE register hold time after clock
LE register clock-to-output delay
LUT delay for data-in to data-out
Table 35. APEX 20KE ESB Timing Microparameters
Symbol
Parameter
t
ESBARC
t
ESBSRC
t
ESBAWC
t
ESBSWC
t
ESBWASU
t
ESBWAH
t
ESBWDSU
t
ESBWDH
t
ESBRASU
t
ESBRAH
t
ESBWESU
t
ESBWEH
t
ESBDATASU
t
ESBDATAH
t
ESBWADDRSU
ESB Asynchronous read cycle time
ESB Synchronous read cycle time
ESB Asynchronous write cycle time
ESB Synchronous write cycle time
ESB write address setup time with respect to WE
ESB write address hold time with respect to WE
ESB data setup time with respect to WE
ESB data hold time with respect to WE
ESB read address setup time with respect to RE
ESB read address hold time with respect to RE
ESB WE setup time before clock when using input register
ESB WE hold time after clock when using input register
ESB data setup time before clock when using input register
ESB data hold time after clock when using input register
ESB write address setup time before clock when using input
registers
ESB read address setup time before clock when using input
registers
ESB clock-to-output delay when using output registers
ESB clock-to-output delay without output registers
ESB data-in to data-out delay for RAM mode
ESB Macrocell input to non-registered output
ESB Macrocell register setup time before clock
ESB Macrocell register clock-to-output delay
t
ESBRADDRSU
t
ESBDATACO1
t
ESBDATACO2
t
ESBDD
t
PD
t
PTERMSU
t
PTERMCO
相关PDF资料
PDF描述
EP20K1000E Programmable Logic Device Family
EP20K100E Programmable Logic Device Family
EP20K1500E Programmable Logic Device Family
EP20K160E Programmable Logic Device Family
EP20K200 Programmable Logic Device Family
相关代理商/技术参数
参数描述
EP20K1000C 制造商:ALTERA 制造商全称:Altera Corporation 功能描述:Programmable Logic
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EP20K1000CB652C7NJ 制造商:Altera Corporation 功能描述:FPGA APEX 20KC Family 1M Gates 38400 Cells 375.94MHz 0.15um (CMOS) Technology 1.8V 652-Pin FCBGA 制造商:Altera Corporation 功能描述:FPGA APEX 20KC Family 1M Gates 38400 Cells 375.94MHz 0.15um Technology 1.8V 652-Pin FCBGA
EP20K1000CB652C8 功能描述:FPGA - 现场可编程门阵列 CPLD - APEX 20K 2560 Macros 488 IO RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256
EP20K1000CB652C9 功能描述:FPGA - 现场可编程门阵列 CPLD - APEX 20K 2560 Macro 488 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256
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