参数资料
型号: EP20K100
厂商: Altera Corporation
英文描述: Programmable Logic Device Family
中文描述: 可编程逻辑器件系列
文件页数: 38/117页
文件大小: 570K
代理商: EP20K100
38
Altera Corporation
APEX 20K Programmable Logic Device Family Data Sheet
Table 10
describes the APEX 20K programmable delays and their logic
options in the Quartus II software.
The Quartus II software compiler can program these delays automatically
to minimize setup time while providing a zero hold time.
Figure 25
shows
how fast bidirectional I/Os are implemented in APEX 20K devices.
The register in the APEX 20K IOE can be programmed to power-up high
or low after configuration is complete. If it is programmed to power-up
low, an asynchronous clear can control the register. If it is programmed to
power-up high, the register cannot be asynchronously cleared or preset.
This feature is useful for cases where the APEX 20K device controls an
active-low input or another device; it prevents inadvertent activation of
the input upon power-up.
Table 10. APEX 20K Programmable Delay Chains
Programmable Delays
Quartus II Logic Option
Input pin to core delay
Input pin to input register delay
Core to output register delay
Output register
t
CO
delay
Decrease input delay to internal cells
Decrease input delay to input register
Decrease input delay to output register
Increase delay to output pin
相关PDF资料
PDF描述
EP20K1000E Programmable Logic Device Family
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