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参数资料
| 型号： | EV-ADF4153SD1Z |
| 厂商： | Analog Devices Inc |
| 文件页数： | 8/24页 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL FOR ADF4153SD1Z |
| 标准包装： | 1 |
| 系列： | * |
ADF4153
Data Sheet
Rev. F | Page 16 of 24
N DIVIDER REGISTER, R0
With R0[1, 0] set to [0, 0], the on-chip N divider register
is programmed. Table 7 shows the input data format for
programming this register.
9-Bit INT Value
These nine bits control what is loaded as the INT value. This is
used to determine the overall feedback division factor. It is used
in Equation 1 (see the INT, FRAC, MOD, and R Relationship
section).
12-Bit FRAC Value
These 12 bits control what is loaded as the FRAC value into the
fractional interpolator. This is part of what determines the
overall feedback division factor. It is also used in Equation 1.
The FRAC value must be less than or equal to the value loaded
into the MOD register.
Fastlock
When set to logic high, fastlock is enabled. This sets the charge
pump current to its maximum value. When set to logic low, the
charge pump current is equal to the value programmed into the
function register. Also, if MUXOUT is programmed to setting
the fastlock switch, MUXOUT is shorted to ground when the
fastlock bit is 1 and is high impedance when this bit is 0.
R DIVIDER REGISTER, R1
With R1[1, 0] set to [0, 1], the on-chip R divider register is
programmed. Table 8 shows the input data format for
programming this register.
Load Control
When set to logic high, the value being programmed in the
modulus is not loaded into the modulus. Instead, it sets the
resync delay of the Σ-Δ. This is done to ensure phase resync
when changing frequencies. See the Phase Resync section for
more information and a worked example.
MUXOUT
The on-chip multiplexer is controlled by DB22, DB21, and
DB20 on the ADF4153. See Table 8 for the truth table.
Digital Lock Detect
The digital lock detect output goes high if there are 24 succes-
sive PFD cycles with an input error of less than 15 ns (for LDP
is 0, see the Control Register, R2 section for a more thorough
explanation of the LDP bit). It stays high until a new channel is
programmed or until the error at the PFD input exceeds 30 ns
for one or more cycles. If the loop bandwidth is narrow compared
to the PFD frequency, the error at the PFD inputs may drop
below 15 ns for 24 cycles around a cycle slip. Therefore, the
digital lock detect may go falsely high for a short period until
the error again exceeds 30 ns. In this case, the digital lock detect
is reliable only as a loss-of-lock detector.
Prescaler (P/P + 1)
The dual-modulus prescaler (P/P + 1), along with the INT,
FRAC, and MOD counters, determines the overall division ratio
from the RFIN to the PFD input.
Operating at CML levels, it takes the clock from the RF input
stage and divides it down for the counters. It is based on a
synchronous 4/5 core. When set to 4/5, the maximum RF
frequency allowed is 2 GHz. Therefore, when operating the
ADF4153 above 2 GHz, this must be set to 8/9. The prescaler
limits the INT value.
With P = 4/5, NMIN = 31.
With P = 8/9, NMIN = 91.
4-Bit R Counter
The 4-bit R counter allows the input reference frequency
(REFIN) to be divided down to produce the reference clock to
the phase frequency detector (PFD). Division ratios from 1 to
15 are allowed.
12-Bit Interpolator MOD Value
These programmable bits set the fractional modulus. This is the
ratio of the PFD frequency to the channel step resolution on the
RF output. Refer to the RF Synthesizer: A Worked Example
section for more information.
The ADF4153 programmable modulus is double buffered. This
means that two events have to occur before the part uses a new
modulus value. First, the new modulus value is latched into the
device by writing to the R divider register. Second, a new write
must be performed on the N divider register. Therefore, any
time that the modulus value has been updated, the N divider
register must then be written to in order to ensure that the
modulus value is loaded correctly.
CONTROL REGISTER, R2
With R2[1, 0] set to [1, 0], the on-chip control register
is programmed. Table 9 shows the input data format for
programming this register.
RF Counter Reset
DB2 is the RF counter reset bit for the ADF4153. When this
is 1, the RF synthesizer counters are held in reset. For normal
operation, this bit should be 0.
RF Charge Pump Three-State
DB3 puts the charge pump into three-state mode when
programmed to 1. It should be set to 0 for normal operation.
RF Power-Down
DB4 on the ADF4153 provides the programmable power-down
mode. Setting this bit to 1 performs a power-down. Setting this
bit to 0 returns the synthesizer to normal operation. While in
software power-down mode, the part retains all information in
its registers. Only when supplies are removed are the register
contents lost.
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