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| 型号： | EVAL-ADAU1761Z |
| 厂商： | Analog Devices Inc |
| 文件页数： | 20/92页 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL FOR ADAU1761 |
| 标准包装： | 1 |
| 系列： | SigmaDSP® |
| 主要目的： | 音频编解码器 |
| 嵌入式： | 是，DSP |
| 已用 IC / 零件： | ADAU1761 |
| 主要属性： | 立体声，24 位，8 ~ 96 kHz 采样率，GUI 工具 |
| 次要属性： | I²C 和 GPIO 接口，2 差分和 1 个立体声单端模拟输入和输出 |
| 已供物品： | 2 个板，线缆，CD |
| 产品目录页面： | 776 (CN2011-ZH PDF) |
| 相关产品： | ADAU1761BCPZ-RL-ND - IC SIGMADSP CODEC PLL 32LFCSP ADAU1761BCPZ-R7-ND - IC SIGMADSP CODEC PLL 32LFCSP ADAU1761BCPZ-ND - IC SIGMADSP CODEC PLL 32LFCSP |
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ADAU1761
Rev. C | Page 27 of 92
SAMPLING RATES
The ADCs, DACs, and serial port share a common sampling
rate that is set in Register R17 (Converter Control 0 register,
Address 0x4017). The CONVSR[2:0] bits set the sampling rate
as a ratio of the base sampling frequency. The DSP sampling
rate is set in Register R57 (DSP sampling rate setting register,
Address 0x40EB) using the DSPSR[3:0] bits, and the serial port
sampling rate is set in Register R64 (serial port sampling rate
register, Address 0x40F8) using the SPSR[2:0] bits.
It is recommended that the sampling rates for the converters,
serial ports, and DSP be set to the same value, unless appropriate
compensation filtering is done within the DSP. Table 13 and
Table 14 list the sampling rate divisions for common base
sampling rates.
Table 13. 48 kHz Base Sampling Rate Divisions
Base Sampling
Frequency
Sampling Rate Scaling
Sampling Rate
fS/1
48 kHz
fS/6
8 kHz
fS/4
12 kHz
fS/3
16 kHz
fS/2
24 kHz
fS/1.5
32 kHz
fS = 48 kHz
fS/0.5
96 kHz
Table 14. 44.1 kHz Base Sampling Rate Divisions
Base Sampling
Frequency
Sampling Rate Scaling
Sampling Rate
fS/1
44.1 kHz
fS/6
7.35 kHz
fS/4
11.025 kHz
fS/3
14.7 kHz
fS/2
22.05 kHz
fS/1.5
29.4 kHz
fS = 44.1 kHz
fS/0.5
88.2 kHz
PLL
The PLL uses the MCLK as a reference to generate the core
clock. PLL settings are set in Register R1 (PLL control register,
Address 0x4002). Depending on the MCLK frequency, the PLL
must be set for either integer or fractional mode. The PLL can
accept input frequencies in the range of 8 MHz to 27 MHz.
All six bytes in the PLL control register must be written with a
single continuous write to the control port.
MCLK
÷ X
× (R + N/M)
TO PLL
CLOCK DIVIDER
07
68
0
-02
1
Figure 31. PLL Block Diagram
Integer Mode
Integer mode is used when the MCLK is an integer (R) multiple
of the PLL output (1024 × fS).
For example, if MCLK = 12.288 MHz and fS = 48 kHz, then
PLL required output = 1024 × 48 kHz = 49.152 MHz
R = 49.152 MHz/12.288 MHz = 4
In integer mode, the values set for N and M are ignored.
Fractional Mode
Fractional mode is used when the MCLK is a fractional
(R + (N/M)) multiple of the PLL output.
For example, if MCLK = 12 MHz and fS = 48 kHz, then
PLL required output = 1024 × 48 kHz = 49.152 MHz
R + (N/M) = 49.152 MHz/12 MHz = 4 + (12/125)
Common fractional PLL parameter settings for 44.1 kHz and
The PLL outputs a clock in the range of 41 MHz to 54 MHz,
which should be taken into account when calculating PLL
values and MCLK frequencies.
Table 15. PLL Control Register (Register R1, Address 0x4002)
Bits
Bit Name
Description
[47:32]
M[15:0]
Denominator of the fractional PLL: 16-bit binary number
0x00FD: M = 253 (default)
[31:16]
N[15:0]
Numerator of the fractional PLL: 16-bit binary number
0x000C: N = 12 (default)
[14:11]
R[3:0]
Integer part of PLL: four bits, only values 2 to 8 are valid
0010: R = 2 (default)
0011: R = 3
0100: R = 4
0101: R = 5
0110: R = 6
0111: R = 7
1000: R = 8
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相关代理商/技术参数 |
参数描述 |
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| EVAL-ADAU1781Z | 功能描述:BOARD EVAL FOR ADAU1781 RoHS:是 类别:编程器，开发系统 >> 评估演示板和套件 系列:SigmaDSP® 标准包装:1 系列:- 主要目的:电信，线路接口单元（LIU） 嵌入式:- 已用 IC / 零件:IDT82V2081 主要属性:T1/J1/E1 LIU 次要属性:- 已供物品:板，电源，线缆，CD 其它名称:82EBV2081 |
| EVAL-ADAU1962AZ | 制造商:Analog Devices 功能描述:EVAL BOARD FOR ADAU1962A - Boxed Product (Development Kits) 制造商:Analog Devices 功能描述:Eval Board for ADAU1962A |
| EVAL-ADAU1966AZ | 制造商:Analog Devices 功能描述:EVAL BOARD FOR ADAU1962A - Boxed Product (Development Kits) |
| EVAL-ADAU1966Z | 功能描述:BOARD EVAL FOR ADAU1966 RoHS:是 类别:编程器，开发系统 >> 评估板 - 数模转换器 (DAC) 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:1 系列:- DAC 的数量:4 位数:12 采样率（每秒）:- 数据接口:串行，SPI? 设置时间:3µs DAC 型:电流/电压 工作温度:-40°C ~ 85°C 已供物品:板 已用 IC / 零件:MAX5581 |
| EVAL-ADAU1966Z | 制造商:Analog Devices 功能描述:ADAU1966, DAC, SIGMA DELTA, SPI, I2C, EV |
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