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| 型号： | EVAL-ADAU1761Z |
| 厂商： | Analog Devices Inc |
| 文件页数： | 77/92页 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL FOR ADAU1761 |
| 标准包装： | 1 |
| 系列： | SigmaDSP® |
| 主要目的： | 音频编解码器 |
| 嵌入式： | 是，DSP |
| 已用 IC / 零件： | ADAU1761 |
| 主要属性： | 立体声，24 位，8 ~ 96 kHz 采样率，GUI 工具 |
| 次要属性： | I²C 和 GPIO 接口，2 差分和 1 个立体声单端模拟输入和输出 |
| 已供物品： | 2 个板，线缆，CD |
| 产品目录页面： | 776 (CN2011-ZH PDF) |
| 相关产品： | ADAU1761BCPZ-RL-ND - IC SIGMADSP CODEC PLL 32LFCSP ADAU1761BCPZ-R7-ND - IC SIGMADSP CODEC PLL 32LFCSP ADAU1761BCPZ-ND - IC SIGMADSP CODEC PLL 32LFCSP |
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ADAU1761
Rev. C | Page 79 of 92
R42: Jack Detect Pin Control, 16,433 (0x4031)
With IOVDD set to 3.3 V, the low and high drive strengths of the JACKDET/MICIN pin are approximately 2.0 mA and 4.0 mA, respectively.
With IOVDD set to 1.8 V, the low and high drive strengths are approximately 0.8 mA and 1.7 mA, respectively. The optional pull-up/
pull-down resistors are nominally 250 kΩ. When enabled, these pull-up/pull-down resistors set the input signals to a defined state when
the signal source becomes three-state.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reserved
JDSTR
Reserved
JDP[1:0]
Reserved
Table 76. Jack Detect Pin Control Register
Bits
Bit Name
Description
5
JDSTR
JACKDET/MICIN pin drive strength.
0 = low (default).
1 = high.
[3:2]
JDP[1:0]
JACKDET/MICIN pad pull-up/pull-down configuration.
Setting
Configuration
00
Pull-up
01
Reserved
10
None (default)
11
Pull-down
R67: Dejitter Control, 16,438 (0x4036)
The dejitter control register allows the size of the dejitter window to be set, and also allows all dejitter circuits in the device to be activated or
bypassed. Dejitter circuits protect against duplicate samples or skipped samples due to jitter from the serial ports in slave mode. Disabling
and reenabling certain subsystems in the device—that is, the ADCs, serial ports, SigmaDSP core, and DACs—during operation can cause
the associated dejitter circuits to fail. As a result, audio data fails to be output to the next subsystem in the device.
When the serial ports are in master mode, the dejitter circuit can be bypassed by setting the dejitter window to 0. When the serial ports
are in slave mode, the dejitter circuit can be reinitialized prior to outputting audio from the device, guaranteeing that audio is output to
the next subsystem in the device. Any time that audio must pass through the ADCs, serial port, sound engine/DSP core, or DACs, the
dejitter circuit can be bypassed and reset by setting the dejitter window size to 0. In this way, the dejitter circuit can be immediately
reactivated, without a wait period, by setting the dejitter window size to the default value of 3.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
DEJIT[7:0]
Table 77. Dejitter Control Register
Bits
Bit Name
Description
[7:0]
DEJIT[7:0]
Dejitter window size.
Window Size
Core Clock Cycles
00000000
0
…
00000011
3 (default)
…
00000101
5
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| EVAL-ADAU1781Z | 功能描述:BOARD EVAL FOR ADAU1781 RoHS:是 类别:编程器，开发系统 >> 评估演示板和套件 系列:SigmaDSP® 标准包装:1 系列:- 主要目的:电信，线路接口单元（LIU） 嵌入式:- 已用 IC / 零件:IDT82V2081 主要属性:T1/J1/E1 LIU 次要属性:- 已供物品:板，电源，线缆，CD 其它名称:82EBV2081 |
| EVAL-ADAU1962AZ | 制造商:Analog Devices 功能描述:EVAL BOARD FOR ADAU1962A - Boxed Product (Development Kits) 制造商:Analog Devices 功能描述:Eval Board for ADAU1962A |
| EVAL-ADAU1966AZ | 制造商:Analog Devices 功能描述:EVAL BOARD FOR ADAU1962A - Boxed Product (Development Kits) |
| EVAL-ADAU1966Z | 功能描述:BOARD EVAL FOR ADAU1966 RoHS:是 类别:编程器，开发系统 >> 评估板 - 数模转换器 (DAC) 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:1 系列:- DAC 的数量:4 位数:12 采样率（每秒）:- 数据接口:串行，SPI? 设置时间:3µs DAC 型:电流/电压 工作温度:-40°C ~ 85°C 已供物品:板 已用 IC / 零件:MAX5581 |
| EVAL-ADAU1966Z | 制造商:Analog Devices 功能描述:ADAU1966, DAC, SIGMA DELTA, SPI, I2C, EV |
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