- 您现在的位置：买卖IC网 > PDF目录16848 > EVAL-ADAU1761Z (Analog Devices Inc)BOARD EVAL FOR ADAU1761 PDF资料下载
参数资料
| 型号： | EVAL-ADAU1761Z |
| 厂商： | Analog Devices Inc |
| 文件页数： | 7/92页 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL FOR ADAU1761 |
| 标准包装： | 1 |
| 系列： | SigmaDSP® |
| 主要目的： | 音频编解码器 |
| 嵌入式： | 是，DSP |
| 已用 IC / 零件： | ADAU1761 |
| 主要属性： | 立体声，24 位，8 ~ 96 kHz 采样率，GUI 工具 |
| 次要属性： | I²C 和 GPIO 接口，2 差分和 1 个立体声单端模拟输入和输出 |
| 已供物品： | 2 个板，线缆，CD |
| 产品目录页面： | 776 (CN2011-ZH PDF) |
| 相关产品： | ADAU1761BCPZ-RL-ND - IC SIGMADSP CODEC PLL 32LFCSP ADAU1761BCPZ-R7-ND - IC SIGMADSP CODEC PLL 32LFCSP ADAU1761BCPZ-ND - IC SIGMADSP CODEC PLL 32LFCSP |
第1页第2页第3页第4页第5页第6页当前第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页第81页第82页第83页第84页第85页第86页第87页第88页第89页第90页第91页第92页
ADAU1761
Rev. C | Page 15 of 92
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
AG
ND
LIN
P
LI
N
RI
NP
RI
NN
RAUX
RO
UT
P
RO
UT
N
S
CL
/CCL
K
S
D
A/
CO
U
T
ADDR
1/
C
DAT
A
L
R
CL
K/
G
P
IO
3
BCL
K/
G
P
IO
2
DAC_S
DAT
A/
G
P
IO
0
ADC_S
DAT
A/
G
P
IO
1
DG
ND
PIN 1
INDICATOR
1
IOVDD
2
MCLK
3
ADDR0/CLATCH
4
JACKDET/MICIN
5
MICBIAS
6
LAUX
7
CM
8
AVDD
24 DVDDOUT
23 AVDD
22 AGND
21 MONOOUT
20 LHP
19 RHP
18 LOUTP
17 LOUTN
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
TOP VIEW
(Not to Scale)
ADAU1761
NOTES
1. THE EXPOSED PAD IS CONNECTED INTERNALLY TO THE
ADAU1761 GROUNDS. FOR INCREASED RELIABILITY OF THE
SOLDER JOINTS AND MAXIMUM THERMAL CAPABILITY, IT IS
RECOMMENDED THAT THE PAD BE SOLDERED TO THE
GROUND PLANE.
07
68
0-
0
07
Figure 7. Pin Configuration
Table 10. Pin Function Descriptions
Pin No.
Mnemonic
Type1
Description
1
IOVDD
PWR
Supply for Digital Input and Output Pins. The digital output pins are supplied from IOVDD,
which also sets the highest input voltage that should be seen on the digital input pins.
IOVDD should be set between 1.8 V and 3.3 V. The current draw of this pin is variable because
it is dependent on the loads of the digital outputs. IOVDD should be decoupled to DGND
with a 100 nF capacitor and a 10 μF capacitor.
2
MCLK
D_IN
External Master Clock Input.
3
ADDR0/CLATCH
D_IN
I2C Address Bit 0 (ADDR0).
SPI Latch Signal (CLATCH). Must go low at the beginning of an SPI transaction and high at the
end of a transaction. Each SPI transaction can take a different number of CCLKs to complete,
depending on the address and read/write bit that are sent at the beginning of the SPI
transaction.
4
JACKDET/MICIN
D_IN
Detect Insertion/Removal of Headphone Plug (JACKDET).
Digital Microphone Stereo Input (MICIN).
5
MICBIAS
A_OUT
Bias Voltage for Electret Microphone.
6
LAUX
A_IN
Left Channel Single-Ended Auxiliary Input. Biased at AVDD/2.
7
CM
A_OUT
AVDD/2 V Common-Mode Reference. A 10 μF to 47 μF standard decoupling capacitor should
be connected between this pin and AGND to reduce crosstalk between the ADCs and DACs.
This pin can be used to bias external analog circuits, as long as they are not drawing current
from CM (for example, the noninverting input of an op amp).
8
AVDD
PWR
1.8 V to 3.65 V Analog Supply for DAC and Microphone Bias. This pin should be decoupled
locally to AGND with a 100 nF capacitor.
9
AGND
PWR
Analog Ground. The AGND and DGND pins can be tied together on a common ground plane.
AGND should be decoupled locally to AVDD with a 100 nF capacitor.
10
LINP
A_IN
Left Channel Noninverting Input or Single-Ended Input 0. Biased at AVDD/2.
11
LINN
A_IN
Left Channel Inverting Input or Single-Ended Input 1. Biased at AVDD/2.
12
RINP
A_IN
Right Channel Noninverting Input or Single-Ended Input 2. Biased at AVDD/2.
13
RINN
A_IN
Right Channel Inverting Input or Single-Ended Input 3. Biased at AVDD/2.
14
RAUX
A_IN
Right Channel Single-Ended Auxiliary Input. Biased at AVDD/2.
15
ROUTP
A_OUT
Right Line Output, Positive. Biased at AVDD/2.
16
ROUTN
A_OUT
Right Line Output, Negative. Biased at AVDD/2.
17
LOUTN
A_OUT
Left Line Output, Negative. Biased at AVDD/2.
18
LOUTP
A_OUT
Left Line Output, Positive. Biased at AVDD/2.
相关PDF资料 |
PDF描述 |
|---|---|
| MAX6174BASA+ | IC VREF SERIES PREC 4.096V 8SOIC |
| GSC06DRXI-S734 | CONN EDGECARD 12POS DIP .100 SLD |
| 0982660987 | CBL 29PS 0.5MM JMPR TYPE A 1.18" |
| SRR5028-680Y | INDUCTOR POWER 68UH 0.62A SMD |
| ADN8831ACPZ-REEL7 | IC THERMO COOLER CTRLR 32LFCSP |
相关代理商/技术参数 |
参数描述 |
|---|---|
| EVAL-ADAU1781Z | 功能描述:BOARD EVAL FOR ADAU1781 RoHS:是 类别:编程器，开发系统 >> 评估演示板和套件 系列:SigmaDSP® 标准包装:1 系列:- 主要目的:电信，线路接口单元（LIU） 嵌入式:- 已用 IC / 零件:IDT82V2081 主要属性:T1/J1/E1 LIU 次要属性:- 已供物品:板，电源，线缆，CD 其它名称:82EBV2081 |
| EVAL-ADAU1962AZ | 制造商:Analog Devices 功能描述:EVAL BOARD FOR ADAU1962A - Boxed Product (Development Kits) 制造商:Analog Devices 功能描述:Eval Board for ADAU1962A |
| EVAL-ADAU1966AZ | 制造商:Analog Devices 功能描述:EVAL BOARD FOR ADAU1962A - Boxed Product (Development Kits) |
| EVAL-ADAU1966Z | 功能描述:BOARD EVAL FOR ADAU1966 RoHS:是 类别:编程器，开发系统 >> 评估板 - 数模转换器 (DAC) 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:1 系列:- DAC 的数量:4 位数:12 采样率（每秒）:- 数据接口:串行，SPI? 设置时间:3µs DAC 型:电流/电压 工作温度:-40°C ~ 85°C 已供物品:板 已用 IC / 零件:MAX5581 |
| EVAL-ADAU1966Z | 制造商:Analog Devices 功能描述:ADAU1966, DAC, SIGMA DELTA, SPI, I2C, EV |
发布紧急采购，3分钟左右您将得到回复。