- 您现在的位置：买卖IC网 > PDF目录16560 > EVAL-ADF4193EBZ2 (Analog Devices Inc)BOARD EVALUATION EB2 FOR ADF4193 PDF资料下载
参数资料
| 型号： | EVAL-ADF4193EBZ2 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 15/32页 |
| 文件大小： | 0K |
| 描述： | BOARD EVALUATION EB2 FOR ADF4193 |
| 标准包装： | 1 |
| 主要目的： | 计时，频率合成器 |
| 嵌入式： | 否 |
| 已用 IC / 零件： | ADF4193 |
| 主要属性： | 400 MHz ~ 3.5 GHz，数字式可编程输出相位 |
| 次要属性： | 板不包括环路滤波器和 VCO |
| 已供物品： | 板，缆线，CD |
| 相关产品： | ADF4193BCPZ-ND - IC PLL FREQ SYNTHESIZER 32LFCSP ADF4193BCPZ-RL7-ND - IC PLL FREQ SYNTHESIZER 32LFCSP ADF4193BCPZ-RL-ND - IC PLL FREQ SYNTHESIZER 32LFCSP |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页当前第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页
ADF4193
Data Sheet
Rev. F | Page 22 of 32
PROGRAMMING
The ADF4193 can synthesize output frequencies with a channel
step or resolution that is a fraction of the input reference frequency.
For a given input reference frequency and a desired output
frequency step, the first choice to make is the PFD reference
frequency and the MOD. Once these are chosen, the desired
output frequency channels are set by programming the INT
and FRAC values.
WORKED EXAMPLE
In this example of a GSM900 RX system, it is required to
generate RF output frequencies with channel steps of 200 kHz.
A 104 MHz reference frequency input (REFIN) is available. The
R divider setting that set the PFD reference is shown in
Equation 1.
FPFD = REFIN × [(1 + D)/(R × (1 + T))]
(1)
where:
REFIN is the input reference frequency.
D is the doubler enable bit (0 or 1).
R is the 4-bit R counter code (0…15).
T is the REF/2 bit (0 or 1).
A PFD frequency of 26 MHz is chosen and the following settings
are programmed to give an R divider value of 4:
Doubler enable = 0
R = 2
REF/2 = 1
Next, the modulus is chosen to allow fractional steps of 200 kHz.
MOD = 26 MHz/200 kHz = 130
(2)
Once the channel step is defined, the following equation shows
how output frequency channels are programmed:
RFOUT = [INT + (FRAC/MOD] × [FPFD]
(3)
where:
RFOUT is the desired RF output frequency.
INT is the integer part of the division.
FRAC is the numerator part of the fractional division.
MOD is the modulus or denominator part of the fractional
division.
For example, the frequency channel at 962.4 MHz is synthesized
by programming the following values:
INT = 37
FRAC = 2
SPUR MECHANISMS
Spurs sections describe the three different spur mechanisms
that arise with a fractional-N synthesizer and how the ADF4193
can be programmed to minimize them.
Fractional Spurs
The fractional interpolator in the ADF4193 is a third-order, Σ-Δ
modulator (SDM) with a modulus (MOD) that is programmable to
any integer value from 13 to 4095. If dither is enabled, then the
minimum allowed value of MOD is 50. The SDM is clocked at
the PFD reference rate (fPFD) that allows PLL output frequencies
to be synthesized at a channel step resolution of fPFD/MOD.
With dither turned off, the quantization noise from the Σ-Δ
modulator appears as fractional spurs. The interval between
spurs is fPFD/L, where L is the repeat length of the code sequence
in the digital Σ-Δ modulator. For the third-order modulator
used in the ADF4193, the repeat length depends on the value of
MOD, as shown in Table 7.
Table 7. Fractional Spurs with Dither Off
Condition (Dither Off)
Repeat Length
Spur Interval
If MOD is divisible by 2,
but not 3
2 × MOD
Channel step/2
If MOD is divisible by 3,
but not 2
3 × MOD
Channel step/3
If MOD is divisible by 6
6 × MOD
Channel step/6
Otherwise
MOD
Channel step
With dither enabled, the repeat length is extended to 221 cycles,
regardless of the value of MOD, which makes the quantization
error spectrum look like broadband noise. This can degrade
the in-band phase noise at the PLL output by as much as 10 dB.
Therefore, for the lowest noise, dither off is a better choice,
particularly when the final loop BW is low enough to attenuate
even the lowest frequency fractional spur. The wide loop
bandwidth range available with the ADF4193 makes this
possible in most applications.
Integer Boundary Spurs
Another mechanism for fractional spur creation involves
interactions between the RF VCO frequency and the reference
frequency. When these frequencies are not integer related, spur
sidebands appear on the VCO output spectrum at an offset
frequency that corresponds to the beat note or difference
frequency between an integer multiple of the reference and the
VCO frequency.
These spurs are attenuated by the loop filter and are more
noticeable on channels close to integer multiples of the refer-
ence where the difference frequency can be inside the loop
bandwidth, thus the name integer boundary spurs.
相关PDF资料 |
PDF描述 |
|---|---|
| RMC06DRTH-S734 | CONN EDGECARD 12POS DIP .100 SLD |
| HBM18DSUN | CONN EDGECARD 36POS .156 DIP SLD |
| RSC06DREI-S734 | CONN EDGECARD 12POS .100 EYELET |
| EBA24DRMI | CONN EDGECARD 48POS .125 SQ WW |
| MAX8663ETL+T | IC PMIC LI+ SNGL CELL 40TQFN |
相关代理商/技术参数 |
参数描述 |
|---|---|
| EVAL-ADF4206-7EB1 | 制造商:Analog Devices 功能描述:EVALUATION BOARD FOR DUAL RF PLL FREQUENCY SYNTHESIZERS 制造商:Analog Devices 功能描述:DUAL RF PLL FREQ SYNTHESIZERS - Bulk |
| EVAL-ADF4208EB1 | 制造商:Analog Devices 功能描述:Evaluation Board For Dual RF PLL Frequency Synthesizers 制造商:Analog Devices 功能描述:DUAL RF PLL FREQ SYNTHESIZERS - Bulk |
| EVAL-ADF4212EB1 | 制造商:Analog Devices 功能描述:EVALUATION BOARD I.C. - Bulk |
| EVAL-ADF4213EB1 | 制造商:Analog Devices 功能描述:EVALUATION BOARD I.C. - Bulk |
| EVAL-ADF4213EB2 | 制造商:Analog Devices 功能描述:EVALUATION BOARD I.C. - Bulk |
发布紧急采购，3分钟左右您将得到回复。