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参数资料
| 型号： | EVAL-ADF4193EBZ2 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 32/32页 |
| 文件大小： | 0K |
| 描述： | BOARD EVALUATION EB2 FOR ADF4193 |
| 标准包装： | 1 |
| 主要目的： | 计时，频率合成器 |
| 嵌入式： | 否 |
| 已用 IC / 零件： | ADF4193 |
| 主要属性： | 400 MHz ~ 3.5 GHz，数字式可编程输出相位 |
| 次要属性： | 板不包括环路滤波器和 VCO |
| 已供物品： | 板，缆线，CD |
| 相关产品： | ADF4193BCPZ-ND - IC PLL FREQ SYNTHESIZER 32LFCSP ADF4193BCPZ-RL7-ND - IC PLL FREQ SYNTHESIZER 32LFCSP ADF4193BCPZ-RL-ND - IC PLL FREQ SYNTHESIZER 32LFCSP |
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Data Sheet
ADF4193
Rev. F | Page 9 of 32
05328-040
TIME (
s)
(V)
–1
0
1
2
3
4
5
9
8
7
6
5
4
3
2
1
0
VTUNE
CPOUT+
CPOUT–
DCS1800 Tx SETUP, 60kHz LOOP BW.
MEASURED ON EVAL-ADF4193-EB1
EVALUATION BOARD.
TIMERS: ICP = 28, SW1/SW2, SW3 = 35.
FREQUENCY LOCK IN WIDE BW MODE @ 4
s.
Figure 10. VTUNE Settling Transient for a 75 MHz Jump from 1818 MHz to
1893 MHz with Sirenza 1843T VCO
05328-008
TIME (
s)
PHASE
ERROR
(Degrees)
–5
0
5
10
15
20
25
30
35
40
–50
50
40
30
20
10
0
–10
–20
–30
–40
45
+25
°C
+85
°C
–40
°C
DCS1800 Tx SETUP, 60kHz LOOP BW.
MEASURED ON EVAL-ADF4193-EB1
EVALUATION BOARD WITH AD8302
PHASE DETECTOR.
TIMERS: ICP = 28, SW1/SW2, SW3 = 35.
PEAK PHASE ERROR < 5
° @ 17.8s
Figure 11. Phase Settling Transient for a 75 MHz Jump from 1818 MHz to
1893 MHz (VTUNE 1.8 V to 3.7 V with Sirenza 1843T VCO)
05328-
012
CPOUT + / CPOUT – VOLTAGE (V)
I CP
(
mA)
M
IS
M
AT
CH
(
%)
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
–8
–6
–4
–2
0
2
4
6
8
–2.0
–1.5
–1.0
–0.5
0
0.5
1.0
1.5
2.0
5.0
ICPOUT + P, ICPOUT – P
CHARGE PUMP MISMATCH (%)
NORMAL OPERATING RANGE
ICPOUT + N, ICPOUT – N
IUP = | ICPOUT + P | + | ICPOUT – N |
IDOWN = | ICPOUT – P | + | ICPOUT + N |
Figure 12. Differential Charge Pump Output Compliance Range and
Charge Pump Mismatch with VP1 = VP2 = 5 V
05328-041
TIME (
s)
(V)
–1
0
1
2
3
4
5
9
8
7
6
5
4
3
2
1
0
VTUNE
CPOUT–
CPOUT+
DCS1800 Tx SETUP, 60kHz LOOP BW.
MEASURED ON EVAL-ADF4193-EB1
EVALUATION BOARD.
TIMERS: ICP = 28, SW1/SW2, SW3 = 35.
FREQUENCY LOCK IN WIDE BW MODE @ 5
s.
Figure 13. VTUNE Settling Transient for a 75 MHz Jump Down from 1893 MHz to
1818 MHz, the Bottom of the Allowed Tuning Range with the Sirenza 1843T VCO
05328-009
TIME (
s)
PHASE
ERROR
(Degrees)
–5
0
5
10
15
20
25
30
35
40
–50
50
40
30
20
10
0
–10
–20
–30
–40
45
+25
°C
+85
°C
–40
°C
DCS1800 Tx SETUP, 60kHz LOOP BW.
MEASURED ON EVAL-ADF4193-EB1
EVALUATION BOARD WITH AD8302
PHASE DETECTOR.
TIMERS: ICP = 28, SW1/SW2, SW3 = 35.
PEAK PHASE ERROR < 5
° @ 19.2s
Figure 14. Phase Settling Transient for a 75 MHz Jump from 1893 MHz to
1818 MHz (VTUNE = 3.7 V to 1.8 V with Sirenza 1843T VCO)
05328-
013
FREQUENCY (MHz)
(V)
1780
1800
1820
1840
1860
1880
1900
1920
1940
0
2
1
3
4
5
VP1 = VP2 = 5V
VP3 = 5.5V
VCMR = 3.3V
CPOUT– (= AIN–)
AOUT (= VTUNE)
CPOUT+ (= AIN+)
Figure 15. Tuning Range with a Sirenza 1843T VCO and a 5.5 V Differential
Amplifier Power Supply Voltage
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