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| 型号： | FDD306P |
| 厂商： | Fairchild Semiconductor |
| 文件页数： | 2/5页 |
| 文件大小： | 0K |
| 描述： | MOSFET P-CH 12V 6.7A DPAK |
| 产品培训模块： | High Voltage Switches for Power Processing |
| 标准包装： | 1 |
| 系列： | PowerTrench® |
| FET 型： | MOSFET P 通道，金属氧化物 |
| FET 特点： | 逻辑电平门 |
| 漏极至源极电压(Vdss)： | 12V |
| 电流 - 连续漏极(Id) @ 25° C： | 6.7A |
| 开态Rds（最大）@ Id, Vgs @ 25° C： | 28 毫欧 @ 6.7A，4.5V |
| Id 时的 Vgs(th)（最大）： | 1.5V @ 250µA |
| 闸电荷(Qg) @ Vgs： | 21nC @ 4.5V |
| 输入电容 (Ciss) @ Vds： | 1290pF @ 6V |
| 功率 - 最大： | 1.6W |
| 安装类型： | 表面贴装 |
| 封装/外壳： | TO-252-3，DPak（2 引线+接片），SC-63 |
| 供应商设备封装： | TO-252-3 |
| 包装： | 标准包装 |
| 其它名称： | FDD306PDKR |
Electrical Characteristics T A = 25°C unless otherwise noted
Symbol
Parameter
Test Conditions
Min
Typ
Max Units
Off Characteristics
BV DSS
? BV DSS
? T J
I DSS
I GSSF
Drain–Source Breakdown Voltage
Breakdown Voltage Temperature Coef?cient
Zero Gate Voltage Drain Current
Gate–Body Leakage
V GS = 0 V, I D = –250 μ A
I D = –250 μ A, Referenced to 25 ° C
V DS = –10 V, V GS = 0 V
V GS = ± 8V, V DS = 0 V
–12
–0.6
–1
± 100
V
mV/ ° C
μ A
nA
On Characteristics (Note 2)
V GS(th)
? V GS(th)
? T J
R DS(on)
Gate Threshold Voltage
Gate Threshold Voltage
Temperature Coef?cient
Static Drain–Source
V DS = V GS , I D = –250 μ A
I D = –250 μ A, Referenced to 25 ° C
V GS = –4.5 V, I D = –6.7 A
–0.4
–0.5
2.2
21
–1.5
28
V
mV/ ° C
m ?
On–Resistance
V GS = –2.5 V, I D = –6.1 A
V GS = –1.8 V, I D = –4.8 A
V GS = –4.5 V, I D = –6.7A, T J = 125 ° C
29
42
25
41
90
I D(on)
g FS
On–State Drain Current
Forward Transconductance
V GS = –4.5 V, V DS = –5 V
V DS = –5 V, I D = –6.7 A
–45
22
A
S
Dynamic Characteristics
C iss
C oss
C rss
R G
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Gate Resistance
V DS = –6 V, V GS = 0 V,
f = 1.0 MHz
V GS = 15 mV, f = 1.0 MHz
1290
590
430
4.2
pF
pF
pF
?
Switching Characteristics (Note 2)
t d(on)
t r
t d(off)
t f
Q g
Q gs
Q gd
Turn–On Delay Time
Turn–On Rise Time
Turn–Off Delay Time
Turn–Off Fall Time
Total Gate Charge
Gate–Source Charge
Gate–Drain Charge
V DD = –6 V, I D = –1 A,
V GS = –4.5 V, R GEN = 6 ?
V DS = –6V, I D = –6.7 A,
V GS = –4.5 V
16
8
34
41
15
2.0
4.4
29
16
54
65
21
ns
ns
ns
ns
nC
nC
nC
Drain–Source Diode Characteristics and Maximum Ratings
I S
Maximum Continuous Drain–Source Diode Forward Current
–3.2
A
V SD
Trr
Irm
Drain–Source Diode Forward Voltage
Diode Reverse Recovery Time
Diode Reverse Recovery Current
V GS = 0 V, I S = –3.2 A
IF = –6.7 A,
diF/dt = 100 A/μs
(Note 2)
(Note 3)
–0.8
37
0.9
–1.2
V
ns
A
Qrr
Diode Reverse Recovery Charge
17
nC
Notes:
1. R θ JA is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is de?ned as the solder mounting surface of the drain pins.
R θ JC is guaranteed by design while R θ CA is determined by the user's board design.
a) R θ JA = 40°C/W when mounted
on a 1in 2 pad of 2 oz copper
Scale 1 : 1 on letter size paper
2. Pulse Test: Pulse Width < 300 μ s, Duty Cycle < 2.0%
b) R θ JA = 96°C/W when mounted on a
minimum pad.
3. Maximum current is calculated as:
P D
------------------------
R DS ( ON )
where P D is maximum power dissipation at T C = 25°C and R DS(on) is at T J(max) and V GS = 10V.
4. Starting T J = 25°C, L = 3 mH, I AS = -4 A, V GS = -10 V, V DD
= -12 V.
FDD306P Rev. C1
2
www.fairchildsemi.com
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