参数资料
型号: FDG6332C
厂商: Fairchild Semiconductor
文件页数: 3/8页
文件大小: 0K
描述: MOSFET N/P-CH 20V SC70-6
产品培训模块: High Voltage Switches for Power Processing
产品变化通告: Mold Compound Change 12/Dec/2007
产品目录绘图: MOSFET SC70-6 Pkg
标准包装: 1
系列: PowerTrench®
FET 型: N 和 P 沟道
FET 特点: 逻辑电平门
漏极至源极电压(Vdss): 20V
电流 - 连续漏极(Id) @ 25° C: 700mA,600mA
开态Rds(最大)@ Id, Vgs @ 25° C: 300 毫欧 @ 700mA,4.5V
Id 时的 Vgs(th)(最大): 1.5V @ 250µA
闸电荷(Qg) @ Vgs: 1.5nC @ 4.5V
输入电容 (Ciss) @ Vds: 113pF @ 10V
功率 - 最大: 300mW
安装类型: 表面贴装
封装/外壳: 6-TSSOP,SC-88,SOT-363
供应商设备封装: SC-70-6
包装: 标准包装
产品目录页面: 1608 (CN2011-ZH PDF)
其它名称: FDG6332CDKR
Electrical Characteristics
T A = 25°C unless otherwise noted
Symbol
Parameter
Test Conditions
Min
Typ
Max Units
Drain–Source Diode Characteristics and Maximum Ratings
I S
Maximum Continuous Drain–Source Diode Forward Current
Q1
0.25
A
Q2
–0.25
V SD
Drain–Source Diode Forward
Voltage
Q1
Q2
V GS = 0 V, I S = 0.25 A
V GS = 0 V, I S = –0.25 A
(Note 2)
(Note 2)
0.74
–0.77
1.2
–1.2
V
Notes:
1. R θ JA is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of
the drain pins. R θ JC is guaranteed by design while R θ JA is determined by the user's board design. R θ JA = 415°C/W when mounted on a minimum pad of FR-4
PCB in a still air environment.
2. Pulse Test: Pulse Width < 300 μ s, Duty Cycle < 2.0%
FDG6332C Rev C2 (W)
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