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| 型号： | FDMA8884 |
| 厂商： | Fairchild Semiconductor |
| 文件页数： | 2/6页 |
| 文件大小： | 0K |
| 描述： | MOSFET N-CH 30V 6.5A 6-MLP 2X2 |
| 标准包装： | 3,000 |
| 系列： | PowerTrench® |
| FET 型： | MOSFET N 通道，金属氧化物 |
| FET 特点： | 逻辑电平门 |
| 漏极至源极电压(Vdss)： | 30V |
| 电流 - 连续漏极(Id) @ 25° C： | 6.5A |
| 开态Rds（最大）@ Id, Vgs @ 25° C： | 23 毫欧 @ 6.5A，10V |
| Id 时的 Vgs(th)（最大）： | 3V @ 250µA |
| 闸电荷(Qg) @ Vgs： | 7.5nC @ 10V |
| 输入电容 (Ciss) @ Vds： | 450pF @ 15V |
| 功率 - 最大： | 700mW |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 6-WFDFN 裸露焊盘 |
| 供应商设备封装： | 6-MLP（2x2） |
| 包装： | 带卷 (TR) |
Electrical Characteristics T J = 25 °C unless otherwise noted
Symbol
Parameter
Test Conditions
Min
Typ
Max
Units
Off Characteristics
BV DSS
Δ BV DS S
Δ T J
I DSS
Drain to Source Breakdown Voltage
Breakdown Voltage Temperature
Coefficient
Zero Gate Voltage Drain Current
I D = 250 μ A, V GS = 0 V
I D = 250 μ A, referenced to 25 °C
V DS = 24 V, V GS = 0 V
30
15
1
V
mV/°C
μ A
I GSS
Gate to Source Leakage Current, Forward V GS = 20 V, V DS = 0 V
100
nA
On Characteristics
V GS(th)
Δ V GS(th )
Δ T J
Gate to Source Threshold Voltage
Gate to Source Threshold Voltage
Temperature Coefficient
V GS = V DS , I D = 250 μ A
I D = 250 μ A, referenced to 25 °C
1.2
1.8
-5
3.0
V
mV/°C
V GS = 10 V, I D = 6.5 A
19
23
r DS(on)
Static Drain to Source On Resistance
V GS = 4.5 V, I D = 6.0 A
25
30
m Ω
V GS = 10 V, I D = 6.5 A, T J = 125 °C
25
30
g FS
Forward Transconductance
V DD = 5 V, I D = 6.5 A
26
S
Dynamic Characteristics
C iss
C oss
C rss
R g
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Gate Resistance
V DS = 15 V, V GS = 0 V,
f = 1 MHz
339
132
18
1.1
450
175
28
pF
pF
pF
Ω
Switching Characteristics
t d(on)
Turn-On Delay Time
5
10
ns
t r
t d(off)
t f
Q g(TOT)
Q gs
Q gd
Rise Time
Turn-Off Delay Time
Fall Time
Total Gate Charge
Total Gate Charge
Total Gate Charge
Gate to Drain “Miller” Charge
V DD = 15 V, I D = 6.5 A,
V GS = 10 V, R GEN = 6 Ω
V GS = 0 V to 10 V
V GS = 0 V to 4.5 V V DD = 15 V
I D = 6.5 A
1
11
1
5.4
2.7
1.0
0.9
10
20
10
7.5
3.7
ns
ns
ns
nC
nC
nC
nC
Drain-Source Diode Characteristics
V SD
t rr
Q rr
Source to Drain Diode Forward Voltage
Reverse Recovery Time
Reverse Recovery Charge
V GS = 0 V, I S = 6.5 A
I F = 6.5 A, di/dt = 100 A/ μ s
(Note 2)
0.86
16
4
1.2
28
10
V
ns
nC
NOTES:
1. R θ JA is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins.
R θ JC is guaranteed by design while R θ CA is determined by the user's board design.
a. 65 °C/W when mounted
on a 1 in 2 pad of 2 oz copper.
b. 180 °C/W when mounted on a
minimum pad of 2 oz copper.
2. Pulse Test: Pulse Width < 300 μ s, Duty cycle < 2.0 %.
3. As an N-ch device, the negative Vgs rating is for low duty cycle pulse occurrence only. No continuous rating is implied.
?2012 Fairchild Semiconductor Corporation
FDMA8884 Rev.C 4
2
www.fairchildsemi.com
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